Initial Commit

test/src/test_module.sv

@@ -0,0 +1,20 @@
+module test_module (
+    input i_clk,
+    input i_rst,
+
+    output logic [31:0] o_count
+);
+
+logic [31:0] counter;
+
+always_ff @(posedge i_clk) begin
+    if (i_rst) begin
+        counter <= '0;
+    end else begin
+        counter <= counter + 1;
+    end
+end
+
+assign o_count = counter;
+
+endmodule