Files
build_fpga/src/build_fpga/vivado/vivado.py
Byron Lathi 5687671f67 Vivado Fixes
add quotes, use sv mode
2025-01-26 15:18:20 -08:00

43 lines
1.6 KiB
Python

import rtl_manifest
import os
def build_nonprj(cfg):
all_sources = rtl_manifest.read_sources(cfg["design_info"]["sources"])
verilog_sources = list(filter(lambda s: (s.endswith(".v") or s.endswith(".sv")), all_sources))
xci_sources = list(filter(lambda s: s.endswith(".xci"), all_sources))
xdc_sources = list(filter(lambda s: s.endswith(".xdc"), all_sources))
top = cfg["design_info"]["top_module"]
part = cfg["device_info"]["device"]
with open("build.tcl", "w") as f:
f.write(f"set outputDir ./nonprojectflow\n")
f.write(f"file mkdir $outputDir\n")
f.write(f"set_part {part}\n")
f.write(f"read_verilog -sv {' '.join(verilog_sources)}\n")
f.write(f"read_ip \"{' '.join(xci_sources)}\"\n")
f.write(f"read_xdc {' '.join(xdc_sources)}\n")
f.write(f"synth_ip [get_ips *]\n")
f.write(f"synth_design -top {top}\n")
f.write(f"write_checkpoint -force $outputDir/post_synth.dcp\n")
f.write(f"report_utilization -file $outputDir/post_synth_util.rpt\n")
f.write(f"opt_design\n")
f.write(f"place_design\n")
f.write(f"write_checkpoint -force $outputDir/post_place.dcp\n")
f.write(f"route_design\n")
f.write(f"write_checkpoint -force $outputDir/post_route.dcp\n")
f.write(f"report_utilization -file $outputDir/post_impl_util.rpt\n")
f.write(f"write_bitstream -force $outputDir/{top}.bit\n")
f.write(f"exit\n")
os.system(f"vivado -mode tcl -source build.tcl")
os.remove("build.tcl")
if __name__ == "__main__":
main()