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Byron Lathi 5687671f67 Vivado Fixes 
add quotes, use sv mode
2025-01-26 15:18:20 -08:00
src/build_fpga
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test
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.gitignore
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.gitlab-ci.yml
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init_env.sh
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LICENSE.txt
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output.xml
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pyproject.toml
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README.md
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requirements.txt
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README.md

Build FPGA

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Description
No description provided
Readme 86 KiB
Languages
Python 90%
SystemVerilog 7.7%
Shell 1.2%
Makefile 1.1%