20 lines
292 B
Systemverilog
20 lines
292 B
Systemverilog
module test_module (
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input i_clk,
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input i_rst,
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output logic [31:0] o_count
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);
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logic [31:0] counter;
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always_ff @(posedge i_clk) begin
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if (i_rst) begin
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counter <= '0;
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end else begin
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counter <= counter + 1;
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end
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end
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assign o_count = counter;
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endmodule |