Add hexdump methods to AXI RAM models

This commit is contained in:
Alex Forencich
2020-11-14 22:47:36 -08:00
parent 9d4b8eb125
commit 4abe02086a
2 changed files with 38 additions and 0 deletions

View File

@@ -32,6 +32,7 @@ from collections import deque
from .constants import *
from .axil_channels import *
from .utils import hexdump, hexdump_str
class AxiLiteRamWrite(object):
@@ -70,6 +71,12 @@ class AxiLiteRamWrite(object):
self.mem.seek(address)
self.mem.write(bytes(data))
def hexdump(self, address, length, prefix=""):
hexdump(self.mem, address, length, prefix=prefix)
def hexdump_str(self, address, length, prefix=""):
return hexdump_str(self.mem, address, length, prefix=prefix)
async def _process_write(self):
while True:
await self.aw_channel.wait()
@@ -140,6 +147,12 @@ class AxiLiteRamRead(object):
self.mem.seek(address)
self.mem.write(bytes(data))
def hexdump(self, address, length, prefix=""):
hexdump(self.mem, address, length, prefix=prefix)
def hexdump_str(self, address, length, prefix=""):
return hexdump_str(self.mem, address, length, prefix=prefix)
async def _process_read(self):
while True:
await self.ar_channel.wait()
@@ -185,3 +198,9 @@ class AxiLiteRam(object):
self.mem.seek(address)
self.mem.write(bytes(data))
def hexdump(self, address, length, prefix=""):
hexdump(self.mem, address, length, prefix=prefix)
def hexdump_str(self, address, length, prefix=""):
return hexdump_str(self.mem, address, length, prefix=prefix)