bslathi19/cocotbext-axi
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Rename byte_width to byte_lanes

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This commit is contained in:
Alex Forencich
2021-04-12 15:08:30 -07:00
parent 8bbabd92df
commit 82853b31ff
6 changed files with 91 additions and 91 deletions
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26
cocotbext/axi/axil_ram.py
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@@ -53,17 +53,17 @@ class AxiLiteRamWrite(Memory, Reset):
self.width = len(self.w_channel.bus.wdata)
self.byte_size = 8
self.byte_width = self.width // self.byte_size
self.strb_mask = 2**self.byte_width-1
self.byte_lanes = self.width // self.byte_size
self.strb_mask = 2**self.byte_lanes-1
self.log.info("AXI lite RAM model configuration:")
self.log.info(" Memory size: %d bytes", len(self.mem))
self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr))
self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes)
assert self.byte_width == len(self.w_channel.bus.wstrb)
assert self.byte_width * self.byte_size == self.width
assert self.byte_lanes == len(self.w_channel.bus.wstrb)
assert self.byte_lanes * self.byte_size == self.width
self._process_write_cr = None
@@ -88,7 +88,7 @@ class AxiLiteRamWrite(Memory, Reset):
while True:
aw = await self.aw_channel.recv()
addr = (int(aw.awaddr) // self.byte_width) * self.byte_width
addr = (int(aw.awaddr) // self.byte_lanes) * self.byte_lanes
prot = AxiProt(aw.awprot)
w = await self.w_channel.recv()
@@ -100,12 +100,12 @@ class AxiLiteRamWrite(Memory, Reset):
self.mem.seek(addr % self.size)
data = data.to_bytes(self.byte_width, 'little')
data = data.to_bytes(self.byte_lanes, 'little')
self.log.info("Write data awaddr: 0x%08x awprot: %s wstrb: 0x%02x data: %s",
addr, prot, strb, ' '.join((f'{c:02x}' for c in data)))
for i in range(self.byte_width):
for i in range(self.byte_lanes):
if strb & (1 << i):
self.mem.write(data[i:i+1])
else:
@@ -135,15 +135,15 @@ class AxiLiteRamRead(Memory, Reset):
self.width = len(self.r_channel.bus.rdata)
self.byte_size = 8
self.byte_width = self.width // self.byte_size
self.byte_lanes = self.width // self.byte_size
self.log.info("AXI lite RAM model configuration:")
self.log.info(" Memory size: %d bytes", len(self.mem))
self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr))
self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes)
assert self.byte_width * self.byte_size == self.width
assert self.byte_lanes * self.byte_size == self.width
self._process_read_cr = None
@@ -167,14 +167,14 @@ class AxiLiteRamRead(Memory, Reset):
while True:
ar = await self.ar_channel.recv()
addr = (int(ar.araddr) // self.byte_width) * self.byte_width
addr = (int(ar.araddr) // self.byte_lanes) * self.byte_lanes
prot = AxiProt(ar.arprot)
# todo latency
self.mem.seek(addr % self.size)
data = self.mem.read(self.byte_width)
data = self.mem.read(self.byte_lanes)
r = self.r_channel._transaction_obj()
r.rdata = int.from_bytes(data, 'little')