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Store parameters

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This commit is contained in:
Alex Forencich
2021-04-12 19:27:38 -07:00
parent 82853b31ff
commit 95e2d5800d
4 changed files with 24 additions and 0 deletions
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6
cocotbext/axi/axi_master.py
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@@ -137,6 +137,9 @@ class TagContextManager:
class AxiMasterWrite(Reset): class AxiMasterWrite(Reset):
def __init__(self, bus, clock, reset=None, reset_active_level=True, max_burst_len=256): def __init__(self, bus, clock, reset=None, reset_active_level=True, max_burst_len=256):
self.bus = bus
self.clock = clock
self.reset = reset
self.log = logging.getLogger(f"cocotb.{bus.aw._entity._name}.{bus.aw._name}") self.log = logging.getLogger(f"cocotb.{bus.aw._entity._name}.{bus.aw._name}")
self.log.info("AXI master (write)") self.log.info("AXI master (write)")
@@ -481,6 +484,9 @@ class AxiMasterWrite(Reset):
class AxiMasterRead(Reset): class AxiMasterRead(Reset):
def __init__(self, bus, clock, reset=None, reset_active_level=True, max_burst_len=256): def __init__(self, bus, clock, reset=None, reset_active_level=True, max_burst_len=256):
self.bus = bus
self.clock = clock
self.reset = reset
self.log = logging.getLogger(f"cocotb.{bus.ar._entity._name}.{bus.ar._name}") self.log = logging.getLogger(f"cocotb.{bus.ar._entity._name}.{bus.ar._name}")
self.log.info("AXI master (read)") self.log.info("AXI master (read)")

6
cocotbext/axi/axi_ram.py
View File

@@ -35,6 +35,9 @@ from .reset import Reset
class AxiRamWrite(Memory, Reset): class AxiRamWrite(Memory, Reset):
def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs): def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
self.bus = bus
self.clock = clock
self.reset = reset
self.log = logging.getLogger(f"cocotb.{bus.aw._entity._name}.{bus.aw._name}") self.log = logging.getLogger(f"cocotb.{bus.aw._entity._name}.{bus.aw._name}")
self.log.info("AXI RAM model (write)") self.log.info("AXI RAM model (write)")
@@ -161,6 +164,9 @@ class AxiRamWrite(Memory, Reset):
class AxiRamRead(Memory, Reset): class AxiRamRead(Memory, Reset):
def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs): def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
self.bus = bus
self.clock = clock
self.reset = reset
self.log = logging.getLogger(f"cocotb.{bus.ar._entity._name}.{bus.ar._name}") self.log = logging.getLogger(f"cocotb.{bus.ar._entity._name}.{bus.ar._name}")
self.log.info("AXI RAM model (read)") self.log.info("AXI RAM model (read)")

6
cocotbext/axi/axil_master.py
View File

@@ -47,6 +47,9 @@ AxiLiteReadResp = namedtuple("AxiLiteReadResp", ["address", "data", "resp"])
class AxiLiteMasterWrite(Reset): class AxiLiteMasterWrite(Reset):
def __init__(self, bus, clock, reset=None, reset_active_level=True): def __init__(self, bus, clock, reset=None, reset_active_level=True):
self.bus = bus
self.clock = clock
self.reset = reset
self.log = logging.getLogger(f"cocotb.{bus.aw._entity._name}.{bus.aw._name}") self.log = logging.getLogger(f"cocotb.{bus.aw._entity._name}.{bus.aw._name}")
self.log.info("AXI lite master (write)") self.log.info("AXI lite master (write)")
@@ -271,6 +274,9 @@ class AxiLiteMasterWrite(Reset):
class AxiLiteMasterRead(Reset): class AxiLiteMasterRead(Reset):
def __init__(self, bus, clock, reset=None, reset_active_level=True): def __init__(self, bus, clock, reset=None, reset_active_level=True):
self.bus = bus
self.clock = clock
self.reset = reset
self.log = logging.getLogger(f"cocotb.{bus.ar._entity._name}.{bus.ar._name}") self.log = logging.getLogger(f"cocotb.{bus.ar._entity._name}.{bus.ar._name}")
self.log.info("AXI lite master (read)") self.log.info("AXI lite master (read)")

6
cocotbext/axi/axil_ram.py
View File

@@ -35,6 +35,9 @@ from .reset import Reset
class AxiLiteRamWrite(Memory, Reset): class AxiLiteRamWrite(Memory, Reset):
def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs): def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
self.bus = bus
self.clock = clock
self.reset = reset
self.log = logging.getLogger(f"cocotb.{bus.aw._entity._name}.{bus.aw._name}") self.log = logging.getLogger(f"cocotb.{bus.aw._entity._name}.{bus.aw._name}")
self.log.info("AXI lite RAM model (write)") self.log.info("AXI lite RAM model (write)")
@@ -119,6 +122,9 @@ class AxiLiteRamWrite(Memory, Reset):
class AxiLiteRamRead(Memory, Reset): class AxiLiteRamRead(Memory, Reset):
def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs): def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
self.bus = bus
self.clock = clock
self.reset = reset
self.log = logging.getLogger(f"cocotb.{bus.ar._entity._name}.{bus.ar._name}") self.log = logging.getLogger(f"cocotb.{bus.ar._entity._name}.{bus.ar._name}")
self.log.info("AXI lite RAM model (read)") self.log.info("AXI lite RAM model (read)")