Make resp and prot signals optional

This commit is contained in:
Alex Forencich
2021-04-12 22:04:22 -07:00
parent e7c3a31eb0
commit bc7edec289
4 changed files with 34 additions and 12 deletions

View File

@@ -26,8 +26,8 @@ from .stream import define_stream
# Write address channel
AxiAWBus, AxiAWTransaction, AxiAWSource, AxiAWSink, AxiAWMonitor = define_stream("AxiAW",
signals=["awid", "awaddr", "awlen", "awsize", "awburst", "awprot", "awvalid", "awready"],
optional_signals=["awlock", "awcache", "awqos", "awregion", "awuser"],
signals=["awid", "awaddr", "awlen", "awsize", "awburst", "awvalid", "awready"],
optional_signals=["awlock", "awcache", "awprot", "awqos", "awregion", "awuser"],
signal_widths={"awlen": 8, "awsize": 3, "awburst": 2, "awlock": 1,
"awcache": 4, "awprot": 3, "awqos": 4, "awregion": 4}
)
@@ -41,23 +41,23 @@ AxiWBus, AxiWTransaction, AxiWSource, AxiWSink, AxiWMonitor = define_stream("Axi
# Write response channel
AxiBBus, AxiBTransaction, AxiBSource, AxiBSink, AxiBMonitor = define_stream("AxiB",
signals=["bid", "bresp", "bvalid", "bready"],
optional_signals=["buser"],
signals=["bid", "bvalid", "bready"],
optional_signals=["bresp", "buser"],
signal_widths={"bresp": 2}
)
# Read address channel
AxiARBus, AxiARTransaction, AxiARSource, AxiARSink, AxiARMonitor = define_stream("AxiAR",
signals=["arid", "araddr", "arlen", "arsize", "arburst", "arprot", "arvalid", "arready"],
optional_signals=["arlock", "arcache", "arqos", "arregion", "aruser"],
signals=["arid", "araddr", "arlen", "arsize", "arburst", "arvalid", "arready"],
optional_signals=["arlock", "arcache", "arprot", "arqos", "arregion", "aruser"],
signal_widths={"arlen": 8, "arsize": 3, "arburst": 2, "arlock": 1,
"arcache": 4, "arprot": 3, "arqos": 4, "arregion": 4}
)
# Read data channel
AxiRBus, AxiRTransaction, AxiRSource, AxiRSink, AxiRMonitor = define_stream("AxiR",
signals=["rid", "rdata", "rresp", "rlast", "rvalid", "rready"],
optional_signals=["ruser"],
signals=["rid", "rdata", "rlast", "rvalid", "rready"],
optional_signals=["rresp", "ruser"],
signal_widths={"rresp": 2, "rlast": 1}
)