Make resp and prot signals optional
This commit is contained in:
@@ -26,8 +26,8 @@ from .stream import define_stream
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# Write address channel
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# Write address channel
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AxiAWBus, AxiAWTransaction, AxiAWSource, AxiAWSink, AxiAWMonitor = define_stream("AxiAW",
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AxiAWBus, AxiAWTransaction, AxiAWSource, AxiAWSink, AxiAWMonitor = define_stream("AxiAW",
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signals=["awid", "awaddr", "awlen", "awsize", "awburst", "awprot", "awvalid", "awready"],
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signals=["awid", "awaddr", "awlen", "awsize", "awburst", "awvalid", "awready"],
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optional_signals=["awlock", "awcache", "awqos", "awregion", "awuser"],
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optional_signals=["awlock", "awcache", "awprot", "awqos", "awregion", "awuser"],
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signal_widths={"awlen": 8, "awsize": 3, "awburst": 2, "awlock": 1,
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signal_widths={"awlen": 8, "awsize": 3, "awburst": 2, "awlock": 1,
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"awcache": 4, "awprot": 3, "awqos": 4, "awregion": 4}
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"awcache": 4, "awprot": 3, "awqos": 4, "awregion": 4}
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)
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)
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@@ -41,23 +41,23 @@ AxiWBus, AxiWTransaction, AxiWSource, AxiWSink, AxiWMonitor = define_stream("Axi
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# Write response channel
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# Write response channel
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AxiBBus, AxiBTransaction, AxiBSource, AxiBSink, AxiBMonitor = define_stream("AxiB",
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AxiBBus, AxiBTransaction, AxiBSource, AxiBSink, AxiBMonitor = define_stream("AxiB",
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signals=["bid", "bresp", "bvalid", "bready"],
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signals=["bid", "bvalid", "bready"],
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optional_signals=["buser"],
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optional_signals=["bresp", "buser"],
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signal_widths={"bresp": 2}
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signal_widths={"bresp": 2}
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)
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)
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# Read address channel
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# Read address channel
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AxiARBus, AxiARTransaction, AxiARSource, AxiARSink, AxiARMonitor = define_stream("AxiAR",
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AxiARBus, AxiARTransaction, AxiARSource, AxiARSink, AxiARMonitor = define_stream("AxiAR",
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signals=["arid", "araddr", "arlen", "arsize", "arburst", "arprot", "arvalid", "arready"],
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signals=["arid", "araddr", "arlen", "arsize", "arburst", "arvalid", "arready"],
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optional_signals=["arlock", "arcache", "arqos", "arregion", "aruser"],
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optional_signals=["arlock", "arcache", "arprot", "arqos", "arregion", "aruser"],
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signal_widths={"arlen": 8, "arsize": 3, "arburst": 2, "arlock": 1,
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signal_widths={"arlen": 8, "arsize": 3, "arburst": 2, "arlock": 1,
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"arcache": 4, "arprot": 3, "arqos": 4, "arregion": 4}
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"arcache": 4, "arprot": 3, "arqos": 4, "arregion": 4}
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)
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)
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# Read data channel
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# Read data channel
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AxiRBus, AxiRTransaction, AxiRSource, AxiRSink, AxiRMonitor = define_stream("AxiR",
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AxiRBus, AxiRTransaction, AxiRSource, AxiRSink, AxiRMonitor = define_stream("AxiR",
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signals=["rid", "rdata", "rresp", "rlast", "rvalid", "rready"],
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signals=["rid", "rdata", "rlast", "rvalid", "rready"],
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optional_signals=["ruser"],
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optional_signals=["rresp", "ruser"],
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signal_widths={"rresp": 2, "rlast": 1}
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signal_widths={"rresp": 2, "rlast": 1}
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)
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)
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@@ -177,6 +177,7 @@ class AxiMasterWrite(Reset):
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self.awlock_present = hasattr(self.bus.aw, "awlock")
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self.awlock_present = hasattr(self.bus.aw, "awlock")
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self.awcache_present = hasattr(self.bus.aw, "awcache")
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self.awcache_present = hasattr(self.bus.aw, "awcache")
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self.awprot_present = hasattr(self.bus.aw, "awprot")
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self.awqos_present = hasattr(self.bus.aw, "awqos")
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self.awqos_present = hasattr(self.bus.aw, "awqos")
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self.awregion_present = hasattr(self.bus.aw, "awregion")
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self.awregion_present = hasattr(self.bus.aw, "awregion")
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self.awuser_present = hasattr(self.bus.aw, "awuser")
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self.awuser_present = hasattr(self.bus.aw, "awuser")
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@@ -240,6 +241,9 @@ class AxiMasterWrite(Reset):
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if not self.awcache_present and cache != 0b0011:
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if not self.awcache_present and cache != 0b0011:
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raise ValueError("awcache sideband signal value specified, but signal is not connected")
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raise ValueError("awcache sideband signal value specified, but signal is not connected")
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if not self.awprot_present and prot != AxiProt.NONSECURE:
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raise ValueError("awprot sideband signal value specified, but signal is not connected")
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if not self.awqos_present and qos != 0:
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if not self.awqos_present and qos != 0:
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raise ValueError("awqos sideband signal value specified, but signal is not connected")
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raise ValueError("awqos sideband signal value specified, but signal is not connected")
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@@ -558,6 +562,7 @@ class AxiMasterRead(Reset):
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self.arlock_present = hasattr(self.bus.ar, "arlock")
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self.arlock_present = hasattr(self.bus.ar, "arlock")
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self.arcache_present = hasattr(self.bus.ar, "arcache")
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self.arcache_present = hasattr(self.bus.ar, "arcache")
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self.arprot_present = hasattr(self.bus.ar, "arprot")
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self.arqos_present = hasattr(self.bus.ar, "arqos")
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self.arqos_present = hasattr(self.bus.ar, "arqos")
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self.arregion_present = hasattr(self.bus.ar, "arregion")
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self.arregion_present = hasattr(self.bus.ar, "arregion")
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self.aruser_present = hasattr(self.bus.ar, "aruser")
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self.aruser_present = hasattr(self.bus.ar, "aruser")
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@@ -622,6 +627,9 @@ class AxiMasterRead(Reset):
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if not self.arcache_present and cache != 0b0011:
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if not self.arcache_present and cache != 0b0011:
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raise ValueError("arcache sideband signal value specified, but signal is not connected")
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raise ValueError("arcache sideband signal value specified, but signal is not connected")
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if not self.arprot_present and prot != AxiProt.NONSECURE:
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raise ValueError("arprot sideband signal value specified, but signal is not connected")
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if not self.arqos_present and qos != 0:
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if not self.arqos_present and qos != 0:
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raise ValueError("arqos sideband signal value specified, but signal is not connected")
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raise ValueError("arqos sideband signal value specified, but signal is not connected")
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@@ -26,7 +26,8 @@ from .stream import define_stream
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# Write address channel
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# Write address channel
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AxiLiteAWBus, AxiLiteAWTransaction, AxiLiteAWSource, AxiLiteAWSink, AxiLiteAWMonitor = define_stream("AxiLiteAW",
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AxiLiteAWBus, AxiLiteAWTransaction, AxiLiteAWSource, AxiLiteAWSink, AxiLiteAWMonitor = define_stream("AxiLiteAW",
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signals=["awaddr", "awprot", "awvalid", "awready"],
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signals=["awaddr", "awvalid", "awready"],
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optional_signals=["awprot"],
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signal_widths={"awprot": 3}
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signal_widths={"awprot": 3}
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)
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)
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@@ -37,19 +38,22 @@ AxiLiteWBus, AxiLiteWTransaction, AxiLiteWSource, AxiLiteWSink, AxiLiteWMonitor
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# Write response channel
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# Write response channel
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AxiLiteBBus, AxiLiteBTransaction, AxiLiteBSource, AxiLiteBSink, AxiLiteBMonitor = define_stream("AxiLiteB",
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AxiLiteBBus, AxiLiteBTransaction, AxiLiteBSource, AxiLiteBSink, AxiLiteBMonitor = define_stream("AxiLiteB",
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signals=["bresp", "bvalid", "bready"],
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signals=["bvalid", "bready"],
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optional_signals=["bresp"],
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signal_widths={"bresp": 2}
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signal_widths={"bresp": 2}
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)
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)
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# Read address channel
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# Read address channel
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AxiLiteARBus, AxiLiteARTransaction, AxiLiteARSource, AxiLiteARSink, AxiLiteARMonitor = define_stream("AxiLiteAR",
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AxiLiteARBus, AxiLiteARTransaction, AxiLiteARSource, AxiLiteARSink, AxiLiteARMonitor = define_stream("AxiLiteAR",
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signals=["araddr", "arprot", "arvalid", "arready"],
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signals=["araddr", "arvalid", "arready"],
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optional_signals=["arprot"],
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signal_widths={"arprot": 3}
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signal_widths={"arprot": 3}
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)
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)
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# Read data channel
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# Read data channel
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AxiLiteRBus, AxiLiteRTransaction, AxiLiteRSource, AxiLiteRSink, AxiLiteRMonitor = define_stream("AxiLiteR",
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AxiLiteRBus, AxiLiteRTransaction, AxiLiteRSource, AxiLiteRSink, AxiLiteRMonitor = define_stream("AxiLiteR",
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signals=["rdata", "rresp", "rvalid", "rready"],
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signals=["rdata", "rvalid", "rready"],
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optional_signals=["rresp"],
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signal_widths={"rresp": 2}
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signal_widths={"rresp": 2}
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)
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)
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@@ -79,6 +79,8 @@ class AxiLiteMasterWrite(Reset):
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self.byte_lanes = self.width // self.byte_size
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self.byte_lanes = self.width // self.byte_size
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self.strb_mask = 2**self.byte_lanes-1
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self.strb_mask = 2**self.byte_lanes-1
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self.awprot_present = hasattr(self.bus.aw, "awprot")
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self.log.info("AXI lite master configuration:")
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self.log.info("AXI lite master configuration:")
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self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr))
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self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr))
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self.log.info(" Byte size: %d bits", self.byte_size)
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self.log.info(" Byte size: %d bits", self.byte_size)
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@@ -107,6 +109,9 @@ class AxiLiteMasterWrite(Reset):
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if not isinstance(event, Event):
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if not isinstance(event, Event):
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raise ValueError("Expected event object")
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raise ValueError("Expected event object")
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if not self.awprot_present and prot != AxiProt.NONSECURE:
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raise ValueError("awprot sideband signal value specified, but signal is not connected")
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self.in_flight_operations += 1
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self.in_flight_operations += 1
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self._idle.clear()
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self._idle.clear()
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@@ -311,6 +316,8 @@ class AxiLiteMasterRead(Reset):
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self.byte_size = 8
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self.byte_size = 8
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self.byte_lanes = self.width // self.byte_size
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self.byte_lanes = self.width // self.byte_size
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self.arprot_present = hasattr(self.bus.ar, "arprot")
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self.log.info("AXI lite master configuration:")
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self.log.info("AXI lite master configuration:")
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self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr))
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self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr))
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self.log.info(" Byte size: %d bits", self.byte_size)
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self.log.info(" Byte size: %d bits", self.byte_size)
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@@ -338,6 +345,9 @@ class AxiLiteMasterRead(Reset):
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if not isinstance(event, Event):
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if not isinstance(event, Event):
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raise ValueError("Expected event object")
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raise ValueError("Expected event object")
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if not self.arprot_present and prot != AxiProt.NONSECURE:
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raise ValueError("arprot sideband signal value specified, but signal is not connected")
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self.in_flight_operations += 1
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self.in_flight_operations += 1
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self._idle.clear()
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self._idle.clear()
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