bslathi19/cocotbext-axi
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Bring out address and ID signal widths

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This commit is contained in:
Alex Forencich
2021-11-10 21:56:08 -08:00
parent d874d91d05
commit c08f22c710
4 changed files with 24 additions and 12 deletions
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6
cocotbext/axi/axil_master.py
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@@ -111,6 +111,7 @@ class AxiLiteMasterWrite(Reset):
self._idle = Event()
self._idle.set()
self.address_width = len(self.aw_channel.bus.awaddr)
self.width = len(self.w_channel.bus.wdata)
self.byte_size = 8
self.byte_lanes = self.width // self.byte_size
@@ -119,7 +120,7 @@ class AxiLiteMasterWrite(Reset):
self.awprot_present = hasattr(self.bus.aw, "awprot")
self.log.info("AXI lite master configuration:")
self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr))
self.log.info(" Address width: %d bits", self.address_width)
self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes)
@@ -350,6 +351,7 @@ class AxiLiteMasterRead(Reset):
self._idle = Event()
self._idle.set()
self.address_width = len(self.ar_channel.bus.araddr)
self.width = len(self.r_channel.bus.rdata)
self.byte_size = 8
self.byte_lanes = self.width // self.byte_size
@@ -357,7 +359,7 @@ class AxiLiteMasterRead(Reset):
self.arprot_present = hasattr(self.bus.ar, "arprot")
self.log.info("AXI lite master configuration:")
self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr))
self.log.info(" Address width: %d bits", self.address_width)
self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_lanes)