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Log model configuration information

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This commit is contained in:
Alex Forencich
2020-11-26 21:15:37 -08:00
parent 7f68f5e73f
commit e5076e700c
5 changed files with 124 additions and 4 deletions
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25
cocotbext/axi/axi_master.py
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@@ -37,7 +37,7 @@ class AxiMasterWrite(object):
def __init__(self, entity, name, clock, reset=None, max_burst_len=256):
self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
self.log.info("AXI master model")
self.log.info("AXI master (write)")
self.log.info("cocotbext-axi version %s", __version__)
self.log.info("Copyright (c) 2020 Alex Forencich")
self.log.info("https://github.com/alexforencich/cocotbext-axi")
@@ -73,6 +73,15 @@ class AxiMasterWrite(object):
self.max_burst_len = max(min(max_burst_len, 256), 1)
self.max_burst_size = (self.byte_width-1).bit_length()
self.log.info("AXI master configuration:")
self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr))
self.log.info(" ID width: %d bits", len(self.aw_channel.bus.awid))
self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width)
self.log.info(" Max burst size: %d (%d bytes)", self.max_burst_size, 2**self.max_burst_size)
self.log.info(" Max burst length: %d cycles (%d bytes)",
self.max_burst_len, self.max_burst_len*self.byte_width)
assert self.byte_width == len(self.w_channel.bus.wstrb)
assert self.byte_width * self.byte_size == self.width
@@ -327,6 +336,11 @@ class AxiMasterRead(object):
def __init__(self, entity, name, clock, reset=None, max_burst_len=256):
self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
self.log.info("AXI master (read)")
self.log.info("cocotbext-axi version %s", __version__)
self.log.info("Copyright (c) 2020 Alex Forencich")
self.log.info("https://github.com/alexforencich/cocotbext-axi")
self.reset = reset
self.ar_channel = AxiARSource(entity, name, clock, reset)
@@ -356,6 +370,15 @@ class AxiMasterRead(object):
self.max_burst_len = max(min(max_burst_len, 256), 1)
self.max_burst_size = (self.byte_width-1).bit_length()
self.log.info("AXI master configuration:")
self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr))
self.log.info(" ID width: %d bits", len(self.ar_channel.bus.arid))
self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width)
self.log.info(" Max burst size: %d (%d bytes)", self.max_burst_size, 2**self.max_burst_size)
self.log.info(" Max burst length: %d cycles (%d bytes)",
self.max_burst_len, self.max_burst_len*self.byte_width)
assert self.byte_width * self.byte_size == self.width
assert len(self.r_channel.bus.rid) == len(self.ar_channel.bus.arid)