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Log model configuration information

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This commit is contained in:
Alex Forencich
2020-11-26 21:15:37 -08:00
parent 7f68f5e73f
commit e5076e700c
5 changed files with 124 additions and 4 deletions
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21
cocotbext/axi/axi_ram.py
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@@ -37,7 +37,7 @@ class AxiRamWrite(object):
def __init__(self, entity, name, clock, reset=None, size=1024, mem=None):
self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
self.log.info("AXI RAM model")
self.log.info("AXI RAM model (write)")
self.log.info("cocotbext-axi version %s", __version__)
self.log.info("Copyright (c) 2020 Alex Forencich")
self.log.info("https://github.com/alexforencich/cocotbext-axi")
@@ -61,6 +61,13 @@ class AxiRamWrite(object):
self.byte_width = self.width // self.byte_size
self.strb_mask = 2**self.byte_width-1
self.log.info("AXI RAM model configuration:")
self.log.info(" Memory size: %d bytes", len(self.mem))
self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr))
self.log.info(" ID width: %d bits", len(self.aw_channel.bus.awid))
self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width)
assert self.byte_width == len(self.w_channel.bus.wstrb)
assert self.byte_width * self.byte_size == self.width
@@ -160,6 +167,11 @@ class AxiRamRead(object):
def __init__(self, entity, name, clock, reset=None, size=1024, mem=None):
self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
self.log.info("AXI RAM model (read)")
self.log.info("cocotbext-axi version %s", __version__)
self.log.info("Copyright (c) 2020 Alex Forencich")
self.log.info("https://github.com/alexforencich/cocotbext-axi")
if type(mem) is mmap.mmap:
self.mem = mem
else:
@@ -177,6 +189,13 @@ class AxiRamRead(object):
self.byte_size = 8
self.byte_width = self.width // self.byte_size
self.log.info("AXI RAM model configuration:")
self.log.info(" Memory size: %d bytes", len(self.mem))
self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr))
self.log.info(" ID width: %d bits", len(self.ar_channel.bus.arid))
self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width)
assert self.byte_width * self.byte_size == self.width
assert len(self.r_channel.bus.rid) == len(self.ar_channel.bus.arid)