bslathi19/cocotbext-axi
1
0
Fork 0
Code Issues Actions Packages Projects Releases 5 Wiki Activity

Log model configuration information

Browse Source
This commit is contained in:
Alex Forencich
2020-11-26 21:15:37 -08:00
parent 7f68f5e73f
commit e5076e700c
5 changed files with 124 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
cocotbext/axi/axi_master.py
View File

@@ -37,7 +37,7 @@ class AxiMasterWrite(object):
def __init__(self, entity, name, clock, reset=None, max_burst_len=256):
self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
self.log.info("AXI master model")
self.log.info("AXI master (write)")
self.log.info("cocotbext-axi version %s", __version__)
self.log.info("Copyright (c) 2020 Alex Forencich")
self.log.info("https://github.com/alexforencich/cocotbext-axi")
@@ -73,6 +73,15 @@ class AxiMasterWrite(object):
self.max_burst_len = max(min(max_burst_len, 256), 1)
self.max_burst_size = (self.byte_width-1).bit_length()
self.log.info("AXI master configuration:")
self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr))
self.log.info(" ID width: %d bits", len(self.aw_channel.bus.awid))
self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width)
self.log.info(" Max burst size: %d (%d bytes)", self.max_burst_size, 2**self.max_burst_size)
self.log.info(" Max burst length: %d cycles (%d bytes)",
self.max_burst_len, self.max_burst_len*self.byte_width)
assert self.byte_width == len(self.w_channel.bus.wstrb)
assert self.byte_width * self.byte_size == self.width
@@ -327,6 +336,11 @@ class AxiMasterRead(object):
def __init__(self, entity, name, clock, reset=None, max_burst_len=256):
self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
self.log.info("AXI master (read)")
self.log.info("cocotbext-axi version %s", __version__)
self.log.info("Copyright (c) 2020 Alex Forencich")
self.log.info("https://github.com/alexforencich/cocotbext-axi")
self.reset = reset
self.ar_channel = AxiARSource(entity, name, clock, reset)
@@ -356,6 +370,15 @@ class AxiMasterRead(object):
self.max_burst_len = max(min(max_burst_len, 256), 1)
self.max_burst_size = (self.byte_width-1).bit_length()
self.log.info("AXI master configuration:")
self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr))
self.log.info(" ID width: %d bits", len(self.ar_channel.bus.arid))
self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width)
self.log.info(" Max burst size: %d (%d bytes)", self.max_burst_size, 2**self.max_burst_size)
self.log.info(" Max burst length: %d cycles (%d bytes)",
self.max_burst_len, self.max_burst_len*self.byte_width)
assert self.byte_width * self.byte_size == self.width
assert len(self.r_channel.bus.rid) == len(self.ar_channel.bus.arid)

21
cocotbext/axi/axi_ram.py
View File

@@ -37,7 +37,7 @@ class AxiRamWrite(object):
def __init__(self, entity, name, clock, reset=None, size=1024, mem=None):
self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
self.log.info("AXI RAM model")
self.log.info("AXI RAM model (write)")
self.log.info("cocotbext-axi version %s", __version__)
self.log.info("Copyright (c) 2020 Alex Forencich")
self.log.info("https://github.com/alexforencich/cocotbext-axi")
@@ -61,6 +61,13 @@ class AxiRamWrite(object):
self.byte_width = self.width // self.byte_size
self.strb_mask = 2**self.byte_width-1
self.log.info("AXI RAM model configuration:")
self.log.info(" Memory size: %d bytes", len(self.mem))
self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr))
self.log.info(" ID width: %d bits", len(self.aw_channel.bus.awid))
self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width)
assert self.byte_width == len(self.w_channel.bus.wstrb)
assert self.byte_width * self.byte_size == self.width
@@ -160,6 +167,11 @@ class AxiRamRead(object):
def __init__(self, entity, name, clock, reset=None, size=1024, mem=None):
self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
self.log.info("AXI RAM model (read)")
self.log.info("cocotbext-axi version %s", __version__)
self.log.info("Copyright (c) 2020 Alex Forencich")
self.log.info("https://github.com/alexforencich/cocotbext-axi")
if type(mem) is mmap.mmap:
self.mem = mem
else:
@@ -177,6 +189,13 @@ class AxiRamRead(object):
self.byte_size = 8
self.byte_width = self.width // self.byte_size
self.log.info("AXI RAM model configuration:")
self.log.info(" Memory size: %d bytes", len(self.mem))
self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr))
self.log.info(" ID width: %d bits", len(self.ar_channel.bus.arid))
self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width)
assert self.byte_width * self.byte_size == self.width
assert len(self.r_channel.bus.rid) == len(self.ar_channel.bus.arid)

17
cocotbext/axi/axil_master.py
View File

@@ -37,7 +37,7 @@ class AxiLiteMasterWrite(object):
def __init__(self, entity, name, clock, reset=None):
self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
self.log.info("AXI lite master model")
self.log.info("AXI lite master (write)")
self.log.info("cocotbext-axi version %s", __version__)
self.log.info("Copyright (c) 2020 Alex Forencich")
self.log.info("https://github.com/alexforencich/cocotbext-axi")
@@ -66,6 +66,11 @@ class AxiLiteMasterWrite(object):
self.byte_width = self.width // self.byte_size
self.strb_mask = 2**self.byte_width-1
self.log.info("AXI lite master configuration:")
self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr))
self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width)
assert self.byte_width == len(self.w_channel.bus.wstrb)
assert self.byte_width * self.byte_size == self.width
@@ -239,6 +244,11 @@ class AxiLiteMasterRead(object):
def __init__(self, entity, name, clock, reset=None):
self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
self.log.info("AXI lite master (read)")
self.log.info("cocotbext-axi version %s", __version__)
self.log.info("Copyright (c) 2020 Alex Forencich")
self.log.info("https://github.com/alexforencich/cocotbext-axi")
self.reset = reset
self.ar_channel = AxiLiteARSource(entity, name, clock, reset)
@@ -261,6 +271,11 @@ class AxiLiteMasterRead(object):
self.byte_size = 8
self.byte_width = self.width // self.byte_size
self.log.info("AXI lite master configuration:")
self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr))
self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width)
assert self.byte_width * self.byte_size == self.width
cocotb.fork(self._process_read())

19
cocotbext/axi/axil_ram.py
View File

@@ -37,7 +37,7 @@ class AxiLiteRamWrite(object):
def __init__(self, entity, name, clock, reset=None, size=1024, mem=None):
self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
self.log.info("AXI lite RAM model")
self.log.info("AXI lite RAM model (write)")
self.log.info("cocotbext-axi version %s", __version__)
self.log.info("Copyright (c) 2020 Alex Forencich")
self.log.info("https://github.com/alexforencich/cocotbext-axi")
@@ -61,6 +61,12 @@ class AxiLiteRamWrite(object):
self.byte_width = self.width // self.byte_size
self.strb_mask = 2**self.byte_width-1
self.log.info("AXI lite RAM model configuration:")
self.log.info(" Memory size: %d bytes", len(self.mem))
self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr))
self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width)
assert self.byte_width == len(self.w_channel.bus.wstrb)
assert self.byte_width * self.byte_size == self.width
@@ -119,6 +125,11 @@ class AxiLiteRamRead(object):
def __init__(self, entity, name, clock, reset=None, size=1024, mem=None):
self.log = SimLog("cocotb.%s.%s" % (entity._name, name))
self.log.info("AXI lite RAM model (read)")
self.log.info("cocotbext-axi version %s", __version__)
self.log.info("Copyright (c) 2020 Alex Forencich")
self.log.info("https://github.com/alexforencich/cocotbext-axi")
self.reset = reset
self.ar_channel = AxiLiteARSink(entity, name, clock, reset)
@@ -136,6 +147,12 @@ class AxiLiteRamRead(object):
self.byte_size = 8
self.byte_width = self.width // self.byte_size
self.log.info("AXI lite RAM model configuration:")
self.log.info(" Memory size: %d bytes", len(self.mem))
self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr))
self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width)
assert self.byte_width * self.byte_size == self.width
cocotb.fork(self._process_read())

46
cocotbext/axi/axis.py
View File

@@ -261,6 +261,29 @@ class AxiStreamSource(object):
self.byte_size = self.width // self.byte_width
self.byte_mask = 2**self.byte_size-1
self.log.info("AXI stream source configuration:")
self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width)
self.log.info(" tvalid: %s", "present" if hasattr(self.bus, "tvalid") else "not present")
self.log.info(" tready: %s", "present" if hasattr(self.bus, "tready") else "not present")
self.log.info(" tlast: %s", "present" if hasattr(self.bus, "tlast") else "not present")
if hasattr(self.bus, "tkeep"):
self.log.info(" tkeep width: %d bits", len(self.bus.tkeep))
else:
self.log.info(" tkeep: not present")
if hasattr(self.bus, "tid"):
self.log.info(" tid width: %d bits", len(self.bus.tid))
else:
self.log.info(" tid: not present")
if hasattr(self.bus, "tdest"):
self.log.info(" tdest width: %d bits", len(self.bus.tdest))
else:
self.log.info(" tdest: not present")
if hasattr(self.bus, "tuser"):
self.log.info(" tuser width: %d bits", len(self.bus.tuser))
else:
self.log.info(" tuser: not present")
cocotb.fork(self._run())
def send(self, frame):
@@ -431,6 +454,29 @@ class AxiStreamSink(object):
self.byte_size = self.width // self.byte_width
self.byte_mask = 2**self.byte_size-1
self.log.info("AXI stream sink configuration:")
self.log.info(" Byte size: %d bits", self.byte_size)
self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width)
self.log.info(" tvalid: %s", "present" if hasattr(self.bus, "tvalid") else "not present")
self.log.info(" tready: %s", "present" if hasattr(self.bus, "tready") else "not present")
self.log.info(" tlast: %s", "present" if hasattr(self.bus, "tlast") else "not present")
if hasattr(self.bus, "tkeep"):
self.log.info(" tkeep width: %d bits", len(self.bus.tkeep))
else:
self.log.info(" tkeep: not present")
if hasattr(self.bus, "tid"):
self.log.info(" tid width: %d bits", len(self.bus.tid))
else:
self.log.info(" tid: not present")
if hasattr(self.bus, "tdest"):
self.log.info(" tdest width: %d bits", len(self.bus.tdest))
else:
self.log.info(" tdest: not present")
if hasattr(self.bus, "tuser"):
self.log.info(" tuser width: %d bits", len(self.bus.tuser))
else:
self.log.info(" tuser: not present")
cocotb.fork(self._run())
def recv(self, compact=True):