Change timescale to speed up verilator

2020-11-15 13:09:53 -08:00
parent f258ce0f6a
commit f1648ccf78
9 changed files with 9 additions and 9 deletions
--- a/tests/axil/test_axil.v
+++ b/tests/axil/test_axil.v
@@ -24,7 +24,7 @@ THE SOFTWARE.

 // Language: Verilog 2001

-`timescale 1ns / 1ps
+`timescale 1ns / 1ns

 /*
 * AXI lite test module