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Change timescale to speed up verilator

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This commit is contained in:
Alex Forencich
2020-11-15 13:09:53 -08:00
parent f258ce0f6a
commit f1648ccf78
9 changed files with 9 additions and 9 deletions
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2
tests/axi/Makefile
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@@ -24,7 +24,7 @@ SIM ?= icarus
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
COCOTB_HDL_TIMEPRECISION = 1ns
DUT = test_axi
TOPLEVEL = $(DUT)

2
tests/axi/test_axi.py
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@@ -41,7 +41,7 @@ class TB(object):
def __init__(self, dut):
self.dut = dut
cocotb.fork(Clock(dut.clk, 10, units="ns").start())
cocotb.fork(Clock(dut.clk, 2, units="ns").start())
self.axi_master = AxiMaster(dut, "axi", dut.clk, dut.rst)
self.axi_ram = AxiRam(dut, "axi", dut.clk, dut.rst, size=2**16)

2
tests/axi/test_axi.v
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@@ -24,7 +24,7 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1ns / 1ps
`timescale 1ns / 1ns
/*
* AXI4 test module

2
tests/axil/Makefile
View File

@@ -24,7 +24,7 @@ SIM ?= icarus
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
COCOTB_HDL_TIMEPRECISION = 1ns
DUT = test_axil
TOPLEVEL = $(DUT)

2
tests/axil/test_axil.py
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@@ -40,7 +40,7 @@ class TB(object):
def __init__(self, dut):
self.dut = dut
cocotb.fork(Clock(dut.clk, 10, units="ns").start())
cocotb.fork(Clock(dut.clk, 2, units="ns").start())
self.axil_master = AxiLiteMaster(dut, "axil", dut.clk, dut.rst)
self.axil_ram = AxiLiteRam(dut, "axil", dut.clk, dut.rst, size=2**16)

2
tests/axil/test_axil.v
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@@ -24,7 +24,7 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1ns / 1ps
`timescale 1ns / 1ns
/*
* AXI lite test module

2
tests/axis/Makefile
View File

@@ -24,7 +24,7 @@ SIM ?= icarus
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
COCOTB_HDL_TIMEPRECISION = 1ns
DUT = test_axis
TOPLEVEL = $(DUT)

2
tests/axis/test_axis.py
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@@ -40,7 +40,7 @@ class TB(object):
def __init__(self, dut):
self.dut = dut
cocotb.fork(Clock(dut.clk, 10, units="ns").start())
cocotb.fork(Clock(dut.clk, 2, units="ns").start())
self.source = AxiStreamSource(dut, "axis", dut.clk, dut.rst)
self.sink = AxiStreamSink(dut, "axis", dut.clk, dut.rst)

2
tests/axis/test_axis.v
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@@ -24,7 +24,7 @@ THE SOFTWARE.
// Language: Verilog 2001
`timescale 1ns / 1ps
`timescale 1ns / 1ns
/*
* AXI4-Stream test