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Author SHA1 Message Date
Alex Forencich
432bd81011 Add sparse memory model 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-23 19:27:57 -07:00
Alex Forencich
bde123e05f Add transfer length checks 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-27 16:38:34 -08:00
Alex Forencich
8604017159 For FIXED burst type, issue all bursts with the same starting address 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-27 16:36:04 -08:00
Alex Forencich
e21b9ffcc8 Update ubuntu version in CI 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-12 17:31:31 -08:00
Alex Forencich
47cd74eb6c Rework parameter handling in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 19:50:53 -08:00
Alex Forencich
4bf5945aa3 Bump to dev version 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-25 18:11:44 -08:00
Alex Forencich
f3a7652362 Release v0.1.20 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
v0.1.20 		2023-01-25 17:55:54 -08:00
Alex Forencich
a84ce5447d Put sinks to sleep when idle 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-25 17:46:46 -08:00
Alex Forencich
1c03ec4697 Pass through full address for unaligned operations 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-25 16:27:14 -08:00
Alex Forencich
824eba793d Update package versions 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-24 12:47:15 -08:00
Alex Forencich
a0aad34698 Fix path issue so latest coverage works 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-20 20:57:30 -08:00
Alex Forencich
ede6270ed7 Put source to sleep when there is no data to send 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-20 15:49:16 -08:00
Alex Forencich
cd1a8b47a5 Fix init sequence 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-20 15:48:46 -08:00
Alex Forencich
be6d490adb Cache signal presence 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-20 15:48:23 -08:00
Alex Forencich
39686b849a Update github actions versions 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-20 15:30:32 -08:00
Alex Forencich
706051cb89 Fix tox config and lock package versions 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-20 15:29:11 -08:00
Alex Forencich
3e4f8d7e92 Python 3.6 is EOL; remove from CI tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-18 14:55:25 -08:00
Leon Woestenberg
afae9e69ff Fix AxiStreamFrame default for self.byte_lanes from 1 to all. 
If I connect a AXIS source to an AXIS sink, the #byte_lanes is incorrectly 1 rather than all lanes enabled.
self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "sink"), dut.clk, dut.reset)

Root cause is AxiStreamFrame assumes byte width 1 without TKEEP, but it should default to self.width // 8
because the AXIS specification mentions "when TKEEP is absent, TKEEP defaults to all bits HIGH" and "The width of the data payload is an integer number of bytes."

Fix: https://github.com/alexforencich/cocotbext-axi/blob/master/cocotbext/axi/axis.py#L290

self.byte_lanes = 1
self.byte_lanes = self.width // 8

Relevant AXIS Specification:
https://developer.arm.com/documentation/ihi0051/a/Default-Signaling-Requirements/Default-value-signaling/Optional-TKEEP-and-TSTRB?lang=en

Signed-off-by: Leon Woestenberg <leon@sidebranch.com>
 2023-01-18 12:55:19 -08:00
Alex Forencich
035c1ba803 Support interleaved read data in AXI master 2022-02-01 00:25:01 -08:00
Alex Forencich
873bb1a034 Explicit cast to integer before converting to enum or flag type 2022-01-07 12:52:41 -08:00
Alex Forencich
2d70e5cbe5 Fix AxiLiteSlave wrapper 2022-01-04 15:29:04 -08:00
Alex Forencich
35d9742ae8 Remove extraneous code 2022-01-04 15:28:48 -08:00
Alex Forencich
0f20e2e9bf Bump to dev version 2021-12-28 20:08:44 -08:00
Alex Forencich
7606d7d7bd Release v0.1.18 v0.1.18 2021-12-28 17:23:06 -08:00
Alex Forencich
dd345e87c3 Call write from init_write via start_soon so command FIFO size can be limited 2021-12-27 23:29:29 -08:00
Alex Forencich
9c0592c16a Make wstrb optional 2021-12-27 19:44:30 -08:00
Alex Forencich
8aab5a7294 Support overriding allocated region and window types 2021-12-27 17:58:52 -08:00
Alex Forencich
4f26621e2b Make size optional when creating windows 2021-12-27 17:31:08 -08:00
Alex Forencich
1b6993d80d Use start_soon instead of fork 2021-12-27 17:10:37 -08:00
Alex Forencich
6d9ed8a2d2 Specify min package versions 2021-12-27 17:03:19 -08:00
Alex Forencich
d772b73eb2 Specify min tox and venv versions 2021-12-27 17:02:59 -08:00
Alex Forencich
bd88eda17b Skip missing interpreters 2021-12-27 17:02:39 -08:00
Alex Forencich
53313699a9 Test on Python 3.10 2021-12-27 17:00:44 -08:00
Alex Forencich
3f7193b77c Use start_soon instead of fork 2021-12-08 21:38:12 -08:00
Alex Forencich
2b0b12c68d Cache clock edge event objects 2021-12-03 18:40:04 -08:00
Alex Forencich
4a91212f37 Bump to dev version 2021-11-17 00:06:34 -08:00
Alex Forencich
1608af26e5 Release v0.1.16 v0.1.16 2021-11-16 22:54:37 -08:00
Alex Forencich
31fb855311 Update readme 2021-11-16 22:40:42 -08:00
Alex Forencich
cb4b0e1738 Wrap access on RAM size 2021-11-16 17:13:18 -08:00
Alex Forencich
ea95eeaf0d Don't pass through extra positional args 2021-11-16 17:01:31 -08:00
Alex Forencich
079f4009b3 Rewrite RAM modules to use common slave implementation 2021-11-16 17:00:48 -08:00
Alex Forencich
612a94c97a Add AXI and AXI lite slave modules 2021-11-16 17:00:05 -08:00
Alex Forencich
757e3a6f2d AXI master modules extend Region 2021-11-16 16:58:50 -08:00
Alex Forencich
b9b9a2da72 Add address space abstraction 2021-11-16 16:55:53 -08:00
Alex Forencich
f7660e9038 Add buddy allocator 2021-11-16 16:53:40 -08:00
Alex Forencich
78693a63d5 Fix types 2021-11-10 23:59:11 -08:00
Alex Forencich
34498f6e5d Add write data type check 2021-11-10 23:49:13 -08:00
Alex Forencich
6329187ced Add address range checks 2021-11-10 23:48:47 -08:00
Alex Forencich
da24857dd2 Cast write data to bytes instead of bytearray 2021-11-10 23:45:46 -08:00
Alex Forencich
c08f22c710 Bring out address and ID signal widths 2021-11-10 21:56:08 -08:00