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Wrap access on RAM size

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This commit is contained in:
Alex Forencich
2021-11-16 17:13:18 -08:00
parent ea95eeaf0d
commit cb4b0e1738
2 changed files with 4 additions and 4 deletions
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4
cocotbext/axi/axi_ram.py
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@@ -31,7 +31,7 @@ class AxiRamWrite(AxiSlaveWrite, Memory):
super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
async def _write(self, address, data):
self.write(address, data)
self.write(address % self.size, data)
class AxiRamRead(AxiSlaveRead, Memory):
@@ -39,7 +39,7 @@ class AxiRamRead(AxiSlaveRead, Memory):
super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
async def _read(self, address, length):
return self.read(address, length)
return self.read(address % self.size, length)
class AxiRam(Memory):

4
cocotbext/axi/axil_ram.py
View File

@@ -31,7 +31,7 @@ class AxiLiteRamWrite(AxiLiteSlaveWrite, Memory):
super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
async def _write(self, address, data):
self.write(address, data)
self.write(address % self.size, data)
class AxiLiteRamRead(AxiLiteSlaveRead, Memory):
@@ -39,7 +39,7 @@ class AxiLiteRamRead(AxiLiteSlaveRead, Memory):
super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
async def _read(self, address, length):
return self.read(address, length)
return self.read(address % self.size, length)
class AxiLiteRam(Memory):