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0.1.29
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Byron Lathi
71dc00e850 Fix some cocotb 2.0 warnings
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0.1.29 		2026-02-08 13:12:22 -08:00
Byron Lathi
aa3605a55c Remove extra wait which violated apb spec
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0.1.28 		2026-02-08 00:50:04 -08:00
Byron Lathi
0496147ddf Add deploy
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first_deploy 		2026-02-08 00:38:42 -08:00
Alex Forencich
3e1e7fc1ec Remove extraneous print 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-09-30 11:12:50 -07:00
Alex Forencich
698c29b05f Bump to dev version 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-09-07 15:41:39 -07:00
Alex Forencich
33f510688a Release v0.1.26 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
v0.1.26 		2025-09-07 15:29:50 -07:00
Alex Forencich
da00960112 Update copyright dates 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-09-07 15:28:21 -07:00
Alex Forencich
88b6624a93 Fix X-init for cocotb 2.0 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-09-07 13:13:03 -07:00
Alex Forencich
dcb9a6bd02 Rework reset logic to better handle X/Z 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-09-07 12:56:14 -07:00
Alex Forencich
7136dddd0a Testbench cleanup for cocotb 2.0 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-09-06 22:52:18 -07:00
Alex Forencich
6c15d7d57d Cast to int instead of using .integer 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-09-06 22:25:25 -07:00
Alex Forencich
4595bd8a08 Update envlist 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-09-06 18:28:02 -07:00
Alex Forencich
204ad7a517 Update setup.cfg 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-09-06 18:23:06 -07:00
Alex Forencich
f3dbc07100 Update CI 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-09-06 17:36:54 -07:00
Alex Forencich
a0a5b7ee55 Add APB modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-09-06 17:13:54 -07:00
Alex Forencich
a28ec41f79 Use append instead of extend in AXI lite master 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-09-06 17:04:48 -07:00
Alex Forencich
f2bf8c0ed8 Fix deprecated option name 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-13 13:24:33 -07:00
Alex Forencich
28f4585c08 Clean up sink pause handling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-13 13:20:35 -07:00
Alex Forencich
775301c6fe Cache signal presence in generic stream models 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-13 13:14:32 -07:00
Alex Forencich
39b4ca4a93 Fix logging when using from_entity 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-26 16:45:46 -07:00
Alex Forencich
f70731a8d8 Add Python 3.11 to regression tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-26 16:34:41 -07:00
Alex Forencich
28bc97f226 Remove recursively-expanded macros for module parameters in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-05-26 16:33:34 -07:00
Alex Forencich
e816d6a088 Bump to dev version 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-24 11:05:34 -07:00
Alex Forencich
af377b2c11 Release v0.1.24 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
v0.1.24 		2023-03-24 11:05:02 -07:00
Alex Forencich
cfb52c6130 Fix transfer length checks 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-24 10:06:19 -07:00
Alex Forencich
7e32e584ff Bump to dev version 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-24 01:57:09 -07:00
Alex Forencich
50cf2af49f Release v0.1.22 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
v0.1.22 		2023-03-24 01:31:54 -07:00
Alex Forencich
ddfa1e3c92 Update readme 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-24 01:28:25 -07:00
Alex Forencich
5e8b246159 Use slices to access memory contents to support both mmap and SparseMemory 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-24 01:23:33 -07:00
Alex Forencich
62c2eef4ec Add SparseMemoryRegion object 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-23 23:44:29 -07:00
Alex Forencich
ad6012aea5 Update memory models to use SparseMemory 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-23 23:43:53 -07:00
Alex Forencich
432bd81011 Add sparse memory model 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-03-23 19:27:57 -07:00
Alex Forencich
bde123e05f Add transfer length checks 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-27 16:38:34 -08:00
Alex Forencich
8604017159 For FIXED burst type, issue all bursts with the same starting address 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-27 16:36:04 -08:00
Alex Forencich
e21b9ffcc8 Update ubuntu version in CI 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-12 17:31:31 -08:00
Alex Forencich
47cd74eb6c Rework parameter handling in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-29 19:50:53 -08:00
Alex Forencich
4bf5945aa3 Bump to dev version 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-25 18:11:44 -08:00
Alex Forencich
f3a7652362 Release v0.1.20 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
v0.1.20 		2023-01-25 17:55:54 -08:00
Alex Forencich
a84ce5447d Put sinks to sleep when idle 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-25 17:46:46 -08:00
Alex Forencich
1c03ec4697 Pass through full address for unaligned operations 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-25 16:27:14 -08:00
Alex Forencich
824eba793d Update package versions 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-24 12:47:15 -08:00
Alex Forencich
a0aad34698 Fix path issue so latest coverage works 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-20 20:57:30 -08:00
Alex Forencich
ede6270ed7 Put source to sleep when there is no data to send 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-20 15:49:16 -08:00
Alex Forencich
cd1a8b47a5 Fix init sequence 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-20 15:48:46 -08:00
Alex Forencich
be6d490adb Cache signal presence 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-20 15:48:23 -08:00
Alex Forencich
39686b849a Update github actions versions 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-20 15:30:32 -08:00
Alex Forencich
706051cb89 Fix tox config and lock package versions 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-20 15:29:11 -08:00
Alex Forencich
3e4f8d7e92 Python 3.6 is EOL; remove from CI tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-18 14:55:25 -08:00
Leon Woestenberg
afae9e69ff Fix AxiStreamFrame default for self.byte_lanes from 1 to all. 
If I connect a AXIS source to an AXIS sink, the #byte_lanes is incorrectly 1 rather than all lanes enabled.
self.source = AxiStreamSource(AxiStreamBus.from_prefix(dut, "sink"), dut.clk, dut.reset)

Root cause is AxiStreamFrame assumes byte width 1 without TKEEP, but it should default to self.width // 8
because the AXIS specification mentions "when TKEEP is absent, TKEEP defaults to all bits HIGH" and "The width of the data payload is an integer number of bytes."

Fix: https://github.com/alexforencich/cocotbext-axi/blob/master/cocotbext/axi/axis.py#L290

self.byte_lanes = 1
self.byte_lanes = self.width // 8

Relevant AXIS Specification:
https://developer.arm.com/documentation/ihi0051/a/Default-Signaling-Requirements/Default-value-signaling/Optional-TKEEP-and-TSTRB?lang=en

Signed-off-by: Leon Woestenberg <leon@sidebranch.com>
 2023-01-18 12:55:19 -08:00
Alex Forencich
035c1ba803 Support interleaved read data in AXI master 2022-02-01 00:25:01 -08:00