273 lines
10 KiB
Python
273 lines
10 KiB
Python
"""
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Copyright (c) 2020 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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import logging
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import cocotb
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from .version import __version__
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from .constants import AxiBurstType, AxiProt, AxiResp
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from .axi_channels import AxiAWSink, AxiWSink, AxiBSource, AxiARSink, AxiRSource
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from .memory import Memory
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from .reset import Reset
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class AxiRamWrite(Memory, Reset):
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def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
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self.log = logging.getLogger(f"cocotb.{bus.aw._entity._name}.{bus.aw._name}")
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self.log.info("AXI RAM model (write)")
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self.log.info("cocotbext-axi version %s", __version__)
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self.log.info("Copyright (c) 2020 Alex Forencich")
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self.log.info("https://github.com/alexforencich/cocotbext-axi")
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super().__init__(size, mem, *args, **kwargs)
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self.aw_channel = AxiAWSink(bus.aw, clock, reset, reset_active_level)
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self.w_channel = AxiWSink(bus.w, clock, reset, reset_active_level)
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self.b_channel = AxiBSource(bus.b, clock, reset, reset_active_level)
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self.width = len(self.w_channel.bus.wdata)
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self.byte_size = 8
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self.byte_width = self.width // self.byte_size
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self.strb_mask = 2**self.byte_width-1
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self.log.info("AXI RAM model configuration:")
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self.log.info(" Memory size: %d bytes", len(self.mem))
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self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr))
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self.log.info(" ID width: %d bits", len(self.aw_channel.bus.awid))
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self.log.info(" Byte size: %d bits", self.byte_size)
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self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width)
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assert self.byte_width == len(self.w_channel.bus.wstrb)
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assert self.byte_width * self.byte_size == self.width
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assert len(self.b_channel.bus.bid) == len(self.aw_channel.bus.awid)
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self._process_write_cr = None
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self._init_reset(reset, reset_active_level)
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def _handle_reset(self, state):
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if state:
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self.log.info("Reset asserted")
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if self._process_write_cr is not None:
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self._process_write_cr.kill()
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self._process_write_cr = None
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else:
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self.log.info("Reset de-asserted")
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if self._process_write_cr is None:
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self._process_write_cr = cocotb.scheduler.start_soon(self._process_write())
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self.aw_channel.clear()
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self.w_channel.clear()
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self.b_channel.clear()
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async def _process_write(self):
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while True:
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aw = await self.aw_channel.recv()
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awid = int(aw.awid)
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addr = int(aw.awaddr)
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length = int(aw.awlen)
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size = int(aw.awsize)
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burst = int(aw.awburst)
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prot = AxiProt(int(aw.awprot))
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self.log.info("Write burst awid: 0x%x awaddr: 0x%08x awlen: %d awsize: %d awprot: %s",
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awid, addr, length, size, prot)
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num_bytes = 2**size
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assert 0 < num_bytes <= self.byte_width
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aligned_addr = (addr // num_bytes) * num_bytes
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length += 1
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transfer_size = num_bytes*length
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if burst == AxiBurstType.WRAP:
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lower_wrap_boundary = (addr // transfer_size) * transfer_size
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upper_wrap_boundary = lower_wrap_boundary + transfer_size
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if burst == AxiBurstType.INCR:
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# check 4k boundary crossing
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assert 0x1000-(aligned_addr & 0xfff) >= transfer_size
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cur_addr = aligned_addr
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for n in range(length):
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cur_word_addr = (cur_addr // self.byte_width) * self.byte_width
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w = await self.w_channel.recv()
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data = int(w.wdata)
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strb = int(w.wstrb)
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last = int(w.wlast)
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# todo latency
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self.mem.seek(cur_word_addr % self.size)
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data = data.to_bytes(self.byte_width, 'little')
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self.log.debug("Write word awid: 0x%x addr: 0x%08x wstrb: 0x%02x data: %s",
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awid, cur_addr, strb, ' '.join((f'{c:02x}' for c in data)))
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for i in range(self.byte_width):
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if strb & (1 << i):
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self.mem.write(data[i:i+1])
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else:
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self.mem.seek(1, 1)
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assert last == (n == length-1)
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if burst != AxiBurstType.FIXED:
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cur_addr += num_bytes
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if burst == AxiBurstType.WRAP:
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if cur_addr == upper_wrap_boundary:
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cur_addr = lower_wrap_boundary
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b = self.b_channel._transaction_obj()
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b.bid = awid
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b.bresp = AxiResp.OKAY
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await self.b_channel.send(b)
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class AxiRamRead(Memory, Reset):
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def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
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self.log = logging.getLogger(f"cocotb.{bus.ar._entity._name}.{bus.ar._name}")
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self.log.info("AXI RAM model (read)")
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self.log.info("cocotbext-axi version %s", __version__)
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self.log.info("Copyright (c) 2020 Alex Forencich")
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self.log.info("https://github.com/alexforencich/cocotbext-axi")
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super().__init__(size, mem, *args, **kwargs)
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self.ar_channel = AxiARSink(bus.ar, clock, reset, reset_active_level)
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self.r_channel = AxiRSource(bus.r, clock, reset, reset_active_level)
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self.width = len(self.r_channel.bus.rdata)
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self.byte_size = 8
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self.byte_width = self.width // self.byte_size
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self.log.info("AXI RAM model configuration:")
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self.log.info(" Memory size: %d bytes", len(self.mem))
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self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr))
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self.log.info(" ID width: %d bits", len(self.ar_channel.bus.arid))
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self.log.info(" Byte size: %d bits", self.byte_size)
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self.log.info(" Data width: %d bits (%d bytes)", self.width, self.byte_width)
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assert self.byte_width * self.byte_size == self.width
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assert len(self.r_channel.bus.rid) == len(self.ar_channel.bus.arid)
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self._process_read_cr = None
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self._init_reset(reset, reset_active_level)
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def _handle_reset(self, state):
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if state:
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self.log.info("Reset asserted")
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if self._process_read_cr is not None:
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self._process_read_cr.kill()
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self._process_read_cr = None
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else:
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self.log.info("Reset de-asserted")
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if self._process_read_cr is None:
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self._process_read_cr = cocotb.scheduler.start_soon(self._process_read())
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self.ar_channel.clear()
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self.r_channel.clear()
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async def _process_read(self):
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while True:
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ar = await self.ar_channel.recv()
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arid = int(ar.arid)
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addr = int(ar.araddr)
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length = int(ar.arlen)
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size = int(ar.arsize)
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burst = int(ar.arburst)
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prot = AxiProt(ar.arprot)
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self.log.info("Read burst arid: 0x%x araddr: 0x%08x arlen: %d arsize: %d arprot: %s",
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arid, addr, length, size, prot)
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num_bytes = 2**size
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assert 0 < num_bytes <= self.byte_width
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aligned_addr = (addr // num_bytes) * num_bytes
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length += 1
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transfer_size = num_bytes*length
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if burst == AxiBurstType.WRAP:
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lower_wrap_boundary = (addr // transfer_size) * transfer_size
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upper_wrap_boundary = lower_wrap_boundary + transfer_size
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if burst == AxiBurstType.INCR:
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# check 4k boundary crossing
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assert 0x1000-(aligned_addr & 0xfff) >= transfer_size
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cur_addr = aligned_addr
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for n in range(length):
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cur_word_addr = (cur_addr // self.byte_width) * self.byte_width
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self.mem.seek(cur_word_addr % self.size)
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data = self.mem.read(self.byte_width)
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r = self.r_channel._transaction_obj()
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r.rid = arid
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r.rdata = int.from_bytes(data, 'little')
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r.rlast = n == length-1
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r.rresp = AxiResp.OKAY
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await self.r_channel.send(r)
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self.log.debug("Read word awid: 0x%x addr: 0x%08x data: %s",
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arid, cur_addr, ' '.join((f'{c:02x}' for c in data)))
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if burst != AxiBurstType.FIXED:
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cur_addr += num_bytes
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if burst == AxiBurstType.WRAP:
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if cur_addr == upper_wrap_boundary:
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cur_addr = lower_wrap_boundary
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class AxiRam(Memory):
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def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
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self.write_if = None
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self.read_if = None
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super().__init__(size, mem, *args, **kwargs)
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self.write_if = AxiRamWrite(bus.write, clock, reset, reset_active_level, mem=self.mem)
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self.read_if = AxiRamRead(bus.read, clock, reset, reset_active_level, mem=self.mem)
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