363 lines
12 KiB
Python
363 lines
12 KiB
Python
"""
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Copyright (c) 2020 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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import itertools
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import logging
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import os
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import random
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import cocotb_test.simulator
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import pytest
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge, Timer
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from cocotb.regression import TestFactory
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from cocotbext.axi import AxiBus, AxiMaster, AxiRam
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class TB:
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.fork(Clock(dut.clk, 2, units="ns").start())
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self.axi_master = AxiMaster(AxiBus.from_prefix(dut, "axi"), dut.clk, dut.rst)
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self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "axi"), dut.clk, dut.rst, size=2**16)
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self.axi_ram.write_if.log.setLevel(logging.DEBUG)
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self.axi_ram.read_if.log.setLevel(logging.DEBUG)
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def set_idle_generator(self, generator=None):
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if generator:
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self.axi_master.write_if.aw_channel.set_pause_generator(generator())
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self.axi_master.write_if.w_channel.set_pause_generator(generator())
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self.axi_master.read_if.ar_channel.set_pause_generator(generator())
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self.axi_ram.write_if.b_channel.set_pause_generator(generator())
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self.axi_ram.read_if.r_channel.set_pause_generator(generator())
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def set_backpressure_generator(self, generator=None):
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if generator:
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self.axi_master.write_if.b_channel.set_pause_generator(generator())
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self.axi_master.read_if.r_channel.set_pause_generator(generator())
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self.axi_ram.write_if.aw_channel.set_pause_generator(generator())
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self.axi_ram.write_if.w_channel.set_pause_generator(generator())
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self.axi_ram.read_if.ar_channel.set_pause_generator(generator())
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async def cycle_reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst <= 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst <= 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None, size=None):
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tb = TB(dut)
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byte_width = tb.axi_master.write_if.byte_width
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max_burst_size = tb.axi_master.write_if.max_burst_size
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if size is None:
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size = max_burst_size
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await tb.cycle_reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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for length in list(range(1, byte_width*2))+[1024]:
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for offset in list(range(byte_width))+list(range(4096-byte_width, 4096)):
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tb.log.info("length %d, offset %d", length, offset)
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addr = offset+0x1000
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test_data = bytearray([x % 256 for x in range(length)])
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tb.axi_ram.write(addr-128, b'\xaa'*(length+256))
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await tb.axi_master.write(addr, test_data, size=size)
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tb.log.debug("%s", tb.axi_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48))
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assert tb.axi_ram.read(addr, length) == test_data
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assert tb.axi_ram.read(addr-1, 1) == b'\xaa'
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assert tb.axi_ram.read(addr+length, 1) == b'\xaa'
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None, size=None):
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tb = TB(dut)
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byte_width = tb.axi_master.write_if.byte_width
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max_burst_size = tb.axi_master.write_if.max_burst_size
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if size is None:
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size = max_burst_size
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await tb.cycle_reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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for length in list(range(1, byte_width*2))+[1024]:
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for offset in list(range(byte_width))+list(range(4096-byte_width, 4096)):
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tb.log.info("length %d, offset %d", length, offset)
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addr = offset+0x1000
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test_data = bytearray([x % 256 for x in range(length)])
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tb.axi_ram.write(addr, test_data)
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data = await tb.axi_master.read(addr, length, size=size)
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assert data.data == test_data
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_test_write_words(dut):
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tb = TB(dut)
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byte_width = tb.axi_master.write_if.byte_width
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await tb.cycle_reset()
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for length in list(range(1, 4)):
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for offset in list(range(byte_width)):
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tb.log.info("length %d, offset %d", length, offset)
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addr = offset+0x1000
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test_data = bytearray([x % 256 for x in range(length)])
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event = tb.axi_master.init_write(addr, test_data)
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await event.wait()
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assert tb.axi_ram.read(addr, length) == test_data
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test_data = bytearray([x % 256 for x in range(length)])
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await tb.axi_master.write(addr, test_data)
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assert tb.axi_ram.read(addr, length) == test_data
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test_data = [x * 0x1001 for x in range(length)]
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await tb.axi_master.write_words(addr, test_data)
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assert tb.axi_ram.read_words(addr, length) == test_data
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test_data = [x * 0x10200201 for x in range(length)]
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await tb.axi_master.write_dwords(addr, test_data)
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assert tb.axi_ram.read_dwords(addr, length) == test_data
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test_data = [x * 0x1020304004030201 for x in range(length)]
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await tb.axi_master.write_qwords(addr, test_data)
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assert tb.axi_ram.read_qwords(addr, length) == test_data
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test_data = 0x01*length
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await tb.axi_master.write_byte(addr, test_data)
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assert tb.axi_ram.read_byte(addr) == test_data
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test_data = 0x1001*length
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await tb.axi_master.write_word(addr, test_data)
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assert tb.axi_ram.read_word(addr) == test_data
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test_data = 0x10200201*length
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await tb.axi_master.write_dword(addr, test_data)
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assert tb.axi_ram.read_dword(addr) == test_data
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test_data = 0x1020304004030201*length
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await tb.axi_master.write_qword(addr, test_data)
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assert tb.axi_ram.read_qword(addr) == test_data
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_test_read_words(dut):
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tb = TB(dut)
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byte_width = tb.axi_master.write_if.byte_width
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await tb.cycle_reset()
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for length in list(range(1, 4)):
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for offset in list(range(byte_width)):
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tb.log.info("length %d, offset %d", length, offset)
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addr = offset+0x1000
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test_data = bytearray([x % 256 for x in range(length)])
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tb.axi_ram.write(addr, test_data)
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event = tb.axi_master.init_read(addr, length)
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await event.wait()
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assert event.data.data == test_data
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test_data = bytearray([x % 256 for x in range(length)])
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tb.axi_ram.write(addr, test_data)
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assert (await tb.axi_master.read(addr, length)).data == test_data
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test_data = [x * 0x1001 for x in range(length)]
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tb.axi_ram.write_words(addr, test_data)
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assert await tb.axi_master.read_words(addr, length) == test_data
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test_data = [x * 0x10200201 for x in range(length)]
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tb.axi_ram.write_dwords(addr, test_data)
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assert await tb.axi_master.read_dwords(addr, length) == test_data
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test_data = [x * 0x1020304004030201 for x in range(length)]
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tb.axi_ram.write_qwords(addr, test_data)
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assert await tb.axi_master.read_qwords(addr, length) == test_data
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test_data = 0x01*length
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tb.axi_ram.write_byte(addr, test_data)
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assert await tb.axi_master.read_byte(addr) == test_data
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test_data = 0x1001*length
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tb.axi_ram.write_word(addr, test_data)
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assert await tb.axi_master.read_word(addr) == test_data
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test_data = 0x10200201*length
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tb.axi_ram.write_dword(addr, test_data)
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assert await tb.axi_master.read_dword(addr) == test_data
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test_data = 0x1020304004030201*length
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tb.axi_ram.write_qword(addr, test_data)
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assert await tb.axi_master.read_qword(addr) == test_data
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
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tb = TB(dut)
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await tb.cycle_reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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async def worker(master, offset, aperture, count=16):
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for k in range(count):
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length = random.randint(1, min(512, aperture))
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addr = offset+random.randint(0, aperture-length)
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test_data = bytearray([x % 256 for x in range(length)])
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await Timer(random.randint(1, 100), 'ns')
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await master.write(addr, test_data)
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await Timer(random.randint(1, 100), 'ns')
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data = await master.read(addr, length)
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assert data.data == test_data
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workers = []
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for k in range(16):
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workers.append(cocotb.fork(worker(tb.axi_master, k*0x1000, 0x1000, count=16)))
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while workers:
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await workers.pop(0).join()
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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def cycle_pause():
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return itertools.cycle([1, 1, 1, 0])
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if cocotb.SIM_NAME:
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data_width = len(cocotb.top.axi_wdata)
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byte_width = data_width // 8
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max_burst_size = (byte_width-1).bit_length()
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for test in [run_test_write, run_test_read]:
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factory = TestFactory(test)
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factory.add_option("idle_inserter", [None, cycle_pause])
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factory.add_option("backpressure_inserter", [None, cycle_pause])
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factory.add_option("size", [None]+list(range(max_burst_size)))
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factory.generate_tests()
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for test in [run_test_write_words, run_test_read_words]:
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factory = TestFactory(test)
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factory.generate_tests()
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factory = TestFactory(run_stress_test)
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factory.generate_tests()
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# cocotb-test
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tests_dir = os.path.dirname(__file__)
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@pytest.mark.parametrize("data_width", [8, 16, 32])
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def test_axi(request, data_width):
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dut = "test_axi"
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module = os.path.splitext(os.path.basename(__file__))[0]
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toplevel = dut
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verilog_sources = [
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os.path.join(tests_dir, f"{dut}.v"),
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]
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parameters = {}
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parameters['DATA_WIDTH'] = data_width
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parameters['ADDR_WIDTH'] = 32
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parameters['STRB_WIDTH'] = parameters['DATA_WIDTH'] // 8
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parameters['ID_WIDTH'] = 8
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parameters['AWUSER_WIDTH'] = 1
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parameters['WUSER_WIDTH'] = 1
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parameters['BUSER_WIDTH'] = 1
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parameters['ARUSER_WIDTH'] = 1
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parameters['RUSER_WIDTH'] = 1
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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python_search=[tests_dir],
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verilog_sources=verilog_sources,
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toplevel=toplevel,
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module=module,
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parameters=parameters,
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sim_build=sim_build,
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extra_env=extra_env,
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)
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