Rework sim_build output directory, fix default makefile target

This commit is contained in:
Alex Forencich
2020-12-29 14:25:52 -08:00
parent 16eaea6967
commit 30bc6f68a1
16 changed files with 32 additions and 64 deletions

View File

@@ -31,8 +31,6 @@ TOPLEVEL = $(DUT)
MODULE = $(DUT)
VERILOG_SOURCES += $(DUT).v
SIM_BUILD ?= sim_build_$(MODULE)
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@@ -48,6 +46,8 @@ else ifeq ($(SIM), verilator)
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim
iverilog_dump.v:
echo 'module iverilog_dump();' > $@
echo 'initial begin' >> $@
@@ -57,9 +57,5 @@ iverilog_dump.v:
echo 'endmodule' >> $@
clean::
@rm -rf sim_build_*
@rm -rf iverilog_dump.v
@rm -rf dump.fst $(TOPLEVEL).fst
include $(shell cocotb-config --makefiles)/Makefile.sim

View File

@@ -160,8 +160,8 @@ def test_gmii(request):
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir,
"sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
python_search=[tests_dir],

View File

@@ -31,8 +31,6 @@ TOPLEVEL = $(DUT)
MODULE = $(DUT)
VERILOG_SOURCES += $(DUT).v
SIM_BUILD ?= sim_build_$(MODULE)
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@@ -48,6 +46,8 @@ else ifeq ($(SIM), verilator)
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim
iverilog_dump.v:
echo 'module iverilog_dump();' > $@
echo 'initial begin' >> $@
@@ -57,9 +57,5 @@ iverilog_dump.v:
echo 'endmodule' >> $@
clean::
@rm -rf sim_build_*
@rm -rf iverilog_dump.v
@rm -rf dump.fst $(TOPLEVEL).fst
include $(shell cocotb-config --makefiles)/Makefile.sim

View File

@@ -170,8 +170,8 @@ def test_gmii_phy(request):
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir,
"sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
python_search=[tests_dir],

View File

@@ -31,8 +31,6 @@ TOPLEVEL = $(DUT)
MODULE = $(DUT)
VERILOG_SOURCES += $(DUT).v
SIM_BUILD ?= sim_build_$(MODULE)
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@@ -48,6 +46,8 @@ else ifeq ($(SIM), verilator)
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim
iverilog_dump.v:
echo 'module iverilog_dump();' > $@
echo 'initial begin' >> $@
@@ -57,9 +57,5 @@ iverilog_dump.v:
echo 'endmodule' >> $@
clean::
@rm -rf sim_build_*
@rm -rf iverilog_dump.v
@rm -rf dump.fst $(TOPLEVEL).fst
include $(shell cocotb-config --makefiles)/Makefile.sim

View File

@@ -157,8 +157,8 @@ def test_mii(request):
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir,
"sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
python_search=[tests_dir],

View File

@@ -31,8 +31,6 @@ TOPLEVEL = $(DUT)
MODULE = $(DUT)
VERILOG_SOURCES += $(DUT).v
SIM_BUILD ?= sim_build_$(MODULE)
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@@ -48,6 +46,8 @@ else ifeq ($(SIM), verilator)
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim
iverilog_dump.v:
echo 'module iverilog_dump();' > $@
echo 'initial begin' >> $@
@@ -57,9 +57,5 @@ iverilog_dump.v:
echo 'endmodule' >> $@
clean::
@rm -rf sim_build_*
@rm -rf iverilog_dump.v
@rm -rf dump.fst $(TOPLEVEL).fst
include $(shell cocotb-config --makefiles)/Makefile.sim

View File

@@ -161,8 +161,8 @@ def test_mii_phy(request):
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir,
"sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
python_search=[tests_dir],

View File

@@ -31,8 +31,6 @@ TOPLEVEL = $(DUT)
MODULE = $(DUT)
VERILOG_SOURCES += $(DUT).v
SIM_BUILD ?= sim_build_$(MODULE)
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@@ -48,6 +46,8 @@ else ifeq ($(SIM), verilator)
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim
iverilog_dump.v:
echo 'module iverilog_dump();' > $@
echo 'initial begin' >> $@
@@ -57,9 +57,5 @@ iverilog_dump.v:
echo 'endmodule' >> $@
clean::
@rm -rf sim_build_*
@rm -rf iverilog_dump.v
@rm -rf dump.fst $(TOPLEVEL).fst
include $(shell cocotb-config --makefiles)/Makefile.sim

View File

@@ -310,8 +310,8 @@ def test_ptp_clock(request):
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir,
"sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
python_search=[tests_dir],

View File

@@ -31,8 +31,6 @@ TOPLEVEL = $(DUT)
MODULE = $(DUT)
VERILOG_SOURCES += $(DUT).v
SIM_BUILD ?= sim_build_$(MODULE)
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@@ -48,6 +46,8 @@ else ifeq ($(SIM), verilator)
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim
iverilog_dump.v:
echo 'module iverilog_dump();' > $@
echo 'initial begin' >> $@
@@ -57,9 +57,5 @@ iverilog_dump.v:
echo 'endmodule' >> $@
clean::
@rm -rf sim_build_*
@rm -rf iverilog_dump.v
@rm -rf dump.fst $(TOPLEVEL).fst
include $(shell cocotb-config --makefiles)/Makefile.sim

View File

@@ -157,8 +157,8 @@ def test_rgmii(request):
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir,
"sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
python_search=[tests_dir],

View File

@@ -31,8 +31,6 @@ TOPLEVEL = $(DUT)
MODULE = $(DUT)
VERILOG_SOURCES += $(DUT).v
SIM_BUILD ?= sim_build_$(MODULE)
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@@ -48,6 +46,8 @@ else ifeq ($(SIM), verilator)
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim
iverilog_dump.v:
echo 'module iverilog_dump();' > $@
echo 'initial begin' >> $@
@@ -57,9 +57,5 @@ iverilog_dump.v:
echo 'endmodule' >> $@
clean::
@rm -rf sim_build_*
@rm -rf iverilog_dump.v
@rm -rf dump.fst $(TOPLEVEL).fst
include $(shell cocotb-config --makefiles)/Makefile.sim

View File

@@ -174,8 +174,8 @@ def test_rgmii_phy(request):
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir,
"sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
python_search=[tests_dir],

View File

@@ -35,8 +35,6 @@ VERILOG_SOURCES += $(DUT).v
export PARAM_DATA_WIDTH ?= 64
export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
SIM_BUILD ?= sim_build_$(MODULE)-$(PARAM_DATA_WIDTH)
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@@ -58,6 +56,8 @@ else ifeq ($(SIM), verilator)
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim
iverilog_dump.v:
echo 'module iverilog_dump();' > $@
echo 'initial begin' >> $@
@@ -67,9 +67,5 @@ iverilog_dump.v:
echo 'endmodule' >> $@
clean::
@rm -rf sim_build_*
@rm -rf iverilog_dump.v
@rm -rf dump.fst $(TOPLEVEL).fst
include $(shell cocotb-config --makefiles)/Makefile.sim

View File

@@ -249,8 +249,8 @@ def test_xgmii(request, data_width):
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir,
"sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
python_search=[tests_dir],