Rework sim_build output directory, fix default makefile target
This commit is contained in:
@@ -31,8 +31,6 @@ TOPLEVEL = $(DUT)
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MODULE = $(DUT)
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VERILOG_SOURCES += $(DUT).v
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SIM_BUILD ?= sim_build_$(MODULE)
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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@@ -48,6 +46,8 @@ else ifeq ($(SIM), verilator)
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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iverilog_dump.v:
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echo 'module iverilog_dump();' > $@
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echo 'initial begin' >> $@
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@@ -57,9 +57,5 @@ iverilog_dump.v:
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echo 'endmodule' >> $@
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clean::
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@rm -rf sim_build_*
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@rm -rf iverilog_dump.v
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@rm -rf dump.fst $(TOPLEVEL).fst
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include $(shell cocotb-config --makefiles)/Makefile.sim
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@@ -160,8 +160,8 @@ def test_gmii(request):
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir,
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"sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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python_search=[tests_dir],
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@@ -31,8 +31,6 @@ TOPLEVEL = $(DUT)
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MODULE = $(DUT)
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VERILOG_SOURCES += $(DUT).v
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SIM_BUILD ?= sim_build_$(MODULE)
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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@@ -48,6 +46,8 @@ else ifeq ($(SIM), verilator)
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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iverilog_dump.v:
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echo 'module iverilog_dump();' > $@
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echo 'initial begin' >> $@
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@@ -57,9 +57,5 @@ iverilog_dump.v:
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echo 'endmodule' >> $@
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clean::
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@rm -rf sim_build_*
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@rm -rf iverilog_dump.v
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@rm -rf dump.fst $(TOPLEVEL).fst
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include $(shell cocotb-config --makefiles)/Makefile.sim
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@@ -170,8 +170,8 @@ def test_gmii_phy(request):
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir,
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"sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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python_search=[tests_dir],
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@@ -31,8 +31,6 @@ TOPLEVEL = $(DUT)
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MODULE = $(DUT)
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VERILOG_SOURCES += $(DUT).v
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SIM_BUILD ?= sim_build_$(MODULE)
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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@@ -48,6 +46,8 @@ else ifeq ($(SIM), verilator)
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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iverilog_dump.v:
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echo 'module iverilog_dump();' > $@
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echo 'initial begin' >> $@
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@@ -57,9 +57,5 @@ iverilog_dump.v:
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echo 'endmodule' >> $@
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clean::
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@rm -rf sim_build_*
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@rm -rf iverilog_dump.v
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@rm -rf dump.fst $(TOPLEVEL).fst
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include $(shell cocotb-config --makefiles)/Makefile.sim
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@@ -157,8 +157,8 @@ def test_mii(request):
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir,
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"sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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python_search=[tests_dir],
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@@ -31,8 +31,6 @@ TOPLEVEL = $(DUT)
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MODULE = $(DUT)
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VERILOG_SOURCES += $(DUT).v
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SIM_BUILD ?= sim_build_$(MODULE)
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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@@ -48,6 +46,8 @@ else ifeq ($(SIM), verilator)
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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iverilog_dump.v:
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echo 'module iverilog_dump();' > $@
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echo 'initial begin' >> $@
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@@ -57,9 +57,5 @@ iverilog_dump.v:
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echo 'endmodule' >> $@
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clean::
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@rm -rf sim_build_*
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@rm -rf iverilog_dump.v
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@rm -rf dump.fst $(TOPLEVEL).fst
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include $(shell cocotb-config --makefiles)/Makefile.sim
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@@ -161,8 +161,8 @@ def test_mii_phy(request):
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir,
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"sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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python_search=[tests_dir],
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@@ -31,8 +31,6 @@ TOPLEVEL = $(DUT)
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MODULE = $(DUT)
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VERILOG_SOURCES += $(DUT).v
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SIM_BUILD ?= sim_build_$(MODULE)
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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@@ -48,6 +46,8 @@ else ifeq ($(SIM), verilator)
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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iverilog_dump.v:
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echo 'module iverilog_dump();' > $@
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echo 'initial begin' >> $@
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@@ -57,9 +57,5 @@ iverilog_dump.v:
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echo 'endmodule' >> $@
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clean::
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@rm -rf sim_build_*
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@rm -rf iverilog_dump.v
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@rm -rf dump.fst $(TOPLEVEL).fst
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include $(shell cocotb-config --makefiles)/Makefile.sim
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@@ -310,8 +310,8 @@ def test_ptp_clock(request):
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir,
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"sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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python_search=[tests_dir],
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@@ -31,8 +31,6 @@ TOPLEVEL = $(DUT)
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MODULE = $(DUT)
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VERILOG_SOURCES += $(DUT).v
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SIM_BUILD ?= sim_build_$(MODULE)
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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@@ -48,6 +46,8 @@ else ifeq ($(SIM), verilator)
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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iverilog_dump.v:
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echo 'module iverilog_dump();' > $@
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echo 'initial begin' >> $@
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@@ -57,9 +57,5 @@ iverilog_dump.v:
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echo 'endmodule' >> $@
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clean::
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@rm -rf sim_build_*
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@rm -rf iverilog_dump.v
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@rm -rf dump.fst $(TOPLEVEL).fst
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include $(shell cocotb-config --makefiles)/Makefile.sim
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@@ -157,8 +157,8 @@ def test_rgmii(request):
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir,
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"sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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python_search=[tests_dir],
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@@ -31,8 +31,6 @@ TOPLEVEL = $(DUT)
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MODULE = $(DUT)
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VERILOG_SOURCES += $(DUT).v
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SIM_BUILD ?= sim_build_$(MODULE)
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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@@ -48,6 +46,8 @@ else ifeq ($(SIM), verilator)
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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iverilog_dump.v:
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echo 'module iverilog_dump();' > $@
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echo 'initial begin' >> $@
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@@ -57,9 +57,5 @@ iverilog_dump.v:
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echo 'endmodule' >> $@
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clean::
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@rm -rf sim_build_*
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@rm -rf iverilog_dump.v
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@rm -rf dump.fst $(TOPLEVEL).fst
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include $(shell cocotb-config --makefiles)/Makefile.sim
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@@ -174,8 +174,8 @@ def test_rgmii_phy(request):
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir,
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"sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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python_search=[tests_dir],
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@@ -35,8 +35,6 @@ VERILOG_SOURCES += $(DUT).v
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export PARAM_DATA_WIDTH ?= 64
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export PARAM_CTRL_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
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SIM_BUILD ?= sim_build_$(MODULE)-$(PARAM_DATA_WIDTH)
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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@@ -58,6 +56,8 @@ else ifeq ($(SIM), verilator)
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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iverilog_dump.v:
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echo 'module iverilog_dump();' > $@
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echo 'initial begin' >> $@
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@@ -67,9 +67,5 @@ iverilog_dump.v:
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echo 'endmodule' >> $@
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clean::
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@rm -rf sim_build_*
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@rm -rf iverilog_dump.v
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@rm -rf dump.fst $(TOPLEVEL).fst
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include $(shell cocotb-config --makefiles)/Makefile.sim
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@@ -249,8 +249,8 @@ def test_xgmii(request, data_width):
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extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
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sim_build = os.path.join(tests_dir,
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"sim_build_"+request.node.name.replace('[', '-').replace(']', ''))
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sim_build = os.path.join(tests_dir, "sim_build",
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request.node.name.replace('[', '-').replace(']', ''))
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cocotb_test.simulator.run(
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python_search=[tests_dir],
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