Add missing ready, fix constant endianness

This commit is contained in:
Byron Lathi
2025-07-02 09:39:55 -07:00
parent a617277005
commit 2afe869dee
3 changed files with 15 additions and 13 deletions

View File

@@ -57,7 +57,7 @@ class TB:
data_in.extend(struct.unpack("8I", key.to_bytes(32, "little")))
data_in.extend(struct.unpack("2I", counter.to_bytes(8, "little")))
data_in.extend(struct.unpack("2I", nonce.to_bytes(8, "little")))
data_out = chacha_block(data_in)
await self.expected_queue.put(data_out)
@@ -72,6 +72,8 @@ class TB:
self.dut.i_ready.value = 1
self.dut.i_valid.value = 1
await RisingEdge(self.dut.i_clk)
while not self.dut.o_ready.value == 1:
await RisingEdge(self.dut.i_clk)
self.dut.i_valid.value = 0
async def run_output(self):
@@ -91,7 +93,7 @@ async def test_sanity(dut):
await tb.cycle_reset()
count = 1
count = 200
for i in range(count):
key = random.randint(0, 2**256-1)

View File

@@ -46,7 +46,7 @@ always_ff @(posedge i_clk) begin
initial_state_rptr <= '0;
initial_state_wptr <= '0;
end else begin
if (i_valid) begin
if (i_valid & o_ready) begin
initial_states[initial_state_wptr] <= write_initial_state;
if (initial_state_wptr < PIPE_STAGES-1) begin
initial_state_wptr <= initial_state_wptr + 1;
@@ -73,18 +73,18 @@ always_ff @(posedge i_clk) begin
// We cannot just add state_pre_add and read_initial state
// because the addition needs to be done wordwise, with no
// carries between 32 bit groups.
for (int i = 0; i < 16; i++) begin
for (int i = 0; i < 16; i++) begin : final_add
o_state[i*32 +: 32] <= state_pre_add[i*32 +: 32] + read_initial_state[i*32 +: 32];
end
end
end
always_comb begin
for (int i = 0; i < 4; i++) begin
state[0][32*(3-i) +: 32] = CONSTANT[32*(3-i) +: 32]; // constant is big endian
for (int i = 0; i < 4; i++) begin : constant
state[0][32*i +: 32] = CONSTANT[32*(3-i) +: 32]; // constant is big endian
end
for (int i = 0; i < 8; i++) begin
for (int i = 0; i < 8; i++) begin : key
state[0][32*(i+4) +: 32] = i_key[32*i +: 32];
end
@@ -103,6 +103,8 @@ always_comb begin
original_initial_state = read_initial_state;
end
assign ready[ROUNDS] = i_ready;
generate
for (genvar round = 0; round < ROUNDS; round+=2) begin : ROUND_LOOP

View File

@@ -3,9 +3,7 @@ module chacha20_pipelined_round #(
parameter KEY_SIZE = 256,
parameter COUNTER_SIZE = 64,
parameter NONCE_SIZE = 64,
parameter STATE_SIZE = 512,
parameter ROUNDS = 20,
parameter CONSTANT = 128'h657870616e642033322d62797465206b
parameter STATE_SIZE = 512
)(
input logic i_clk,
input logic i_rst,
@@ -55,15 +53,15 @@ always_comb begin
end
1: begin
`QR_IN(1, 5, 9, 13);
`QR_IN(1, 6, 11, 12);
end
2: begin
`QR_IN(2, 6, 10, 14);
`QR_IN(2, 7, 8, 13);
end
3: begin
`QR_IN(3, 7, 11, 15);
`QR_IN(3, 4, 9, 14);
end
endcase
end else begin