Add missing ready, fix constant endianness
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@@ -57,7 +57,7 @@ class TB:
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data_in.extend(struct.unpack("8I", key.to_bytes(32, "little")))
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data_in.extend(struct.unpack("8I", key.to_bytes(32, "little")))
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data_in.extend(struct.unpack("2I", counter.to_bytes(8, "little")))
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data_in.extend(struct.unpack("2I", counter.to_bytes(8, "little")))
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data_in.extend(struct.unpack("2I", nonce.to_bytes(8, "little")))
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data_in.extend(struct.unpack("2I", nonce.to_bytes(8, "little")))
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data_out = chacha_block(data_in)
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data_out = chacha_block(data_in)
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await self.expected_queue.put(data_out)
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await self.expected_queue.put(data_out)
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@@ -72,6 +72,8 @@ class TB:
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self.dut.i_ready.value = 1
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self.dut.i_ready.value = 1
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self.dut.i_valid.value = 1
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self.dut.i_valid.value = 1
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await RisingEdge(self.dut.i_clk)
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await RisingEdge(self.dut.i_clk)
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while not self.dut.o_ready.value == 1:
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await RisingEdge(self.dut.i_clk)
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self.dut.i_valid.value = 0
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self.dut.i_valid.value = 0
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async def run_output(self):
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async def run_output(self):
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@@ -91,7 +93,7 @@ async def test_sanity(dut):
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await tb.cycle_reset()
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await tb.cycle_reset()
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count = 1
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count = 200
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for i in range(count):
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for i in range(count):
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key = random.randint(0, 2**256-1)
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key = random.randint(0, 2**256-1)
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@@ -46,7 +46,7 @@ always_ff @(posedge i_clk) begin
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initial_state_rptr <= '0;
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initial_state_rptr <= '0;
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initial_state_wptr <= '0;
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initial_state_wptr <= '0;
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end else begin
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end else begin
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if (i_valid) begin
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if (i_valid & o_ready) begin
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initial_states[initial_state_wptr] <= write_initial_state;
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initial_states[initial_state_wptr] <= write_initial_state;
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if (initial_state_wptr < PIPE_STAGES-1) begin
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if (initial_state_wptr < PIPE_STAGES-1) begin
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initial_state_wptr <= initial_state_wptr + 1;
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initial_state_wptr <= initial_state_wptr + 1;
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@@ -73,18 +73,18 @@ always_ff @(posedge i_clk) begin
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// We cannot just add state_pre_add and read_initial state
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// We cannot just add state_pre_add and read_initial state
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// because the addition needs to be done wordwise, with no
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// because the addition needs to be done wordwise, with no
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// carries between 32 bit groups.
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// carries between 32 bit groups.
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for (int i = 0; i < 16; i++) begin
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for (int i = 0; i < 16; i++) begin : final_add
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o_state[i*32 +: 32] <= state_pre_add[i*32 +: 32] + read_initial_state[i*32 +: 32];
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o_state[i*32 +: 32] <= state_pre_add[i*32 +: 32] + read_initial_state[i*32 +: 32];
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end
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end
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end
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end
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end
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end
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always_comb begin
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always_comb begin
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for (int i = 0; i < 4; i++) begin
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for (int i = 0; i < 4; i++) begin : constant
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state[0][32*(3-i) +: 32] = CONSTANT[32*(3-i) +: 32]; // constant is big endian
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state[0][32*i +: 32] = CONSTANT[32*(3-i) +: 32]; // constant is big endian
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end
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end
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for (int i = 0; i < 8; i++) begin
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for (int i = 0; i < 8; i++) begin : key
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state[0][32*(i+4) +: 32] = i_key[32*i +: 32];
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state[0][32*(i+4) +: 32] = i_key[32*i +: 32];
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end
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end
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@@ -103,6 +103,8 @@ always_comb begin
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original_initial_state = read_initial_state;
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original_initial_state = read_initial_state;
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end
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end
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assign ready[ROUNDS] = i_ready;
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generate
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generate
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for (genvar round = 0; round < ROUNDS; round+=2) begin : ROUND_LOOP
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for (genvar round = 0; round < ROUNDS; round+=2) begin : ROUND_LOOP
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@@ -3,9 +3,7 @@ module chacha20_pipelined_round #(
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parameter KEY_SIZE = 256,
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parameter KEY_SIZE = 256,
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parameter COUNTER_SIZE = 64,
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parameter COUNTER_SIZE = 64,
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parameter NONCE_SIZE = 64,
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parameter NONCE_SIZE = 64,
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parameter STATE_SIZE = 512,
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parameter STATE_SIZE = 512
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parameter ROUNDS = 20,
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parameter CONSTANT = 128'h657870616e642033322d62797465206b
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)(
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)(
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input logic i_clk,
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input logic i_clk,
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input logic i_rst,
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input logic i_rst,
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@@ -55,15 +53,15 @@ always_comb begin
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end
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end
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1: begin
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1: begin
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`QR_IN(1, 5, 9, 13);
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`QR_IN(1, 6, 11, 12);
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end
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end
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2: begin
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2: begin
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`QR_IN(2, 6, 10, 14);
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`QR_IN(2, 7, 8, 13);
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end
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end
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3: begin
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3: begin
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`QR_IN(3, 7, 11, 15);
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`QR_IN(3, 4, 9, 14);
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end
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end
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endcase
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endcase
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end else begin
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end else begin
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