Add basic repo
This commit is contained in:
Byron Lathi
@@ -0,0 +1,122 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<efxpt:design_db name="chacha20_timing_test" device_def="Ti375N1156" version="2025.1.110" db_version="20251999" last_change_date="Tue Jun 24 23:45:17 2025" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
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<efxpt:device_info>
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<efxpt:iobank_info>
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<efxpt:iobank name="2A" iostd="1.8 V LVCMOS" is_dyn_voltage="false" mode_sel_name="2A_MODE_SEL"/>
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<efxpt:iobank name="2B" iostd="1.8 V LVCMOS" is_dyn_voltage="false" mode_sel_name="2B_MODE_SEL"/>
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<efxpt:iobank name="2C" iostd="1.8 V LVCMOS" is_dyn_voltage="false" mode_sel_name="2C_MODE_SEL"/>
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<efxpt:iobank name="2D" iostd="1.8 V LVCMOS" is_dyn_voltage="false" mode_sel_name="2D_MODE_SEL"/>
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<efxpt:iobank name="2E" iostd="1.8 V LVCMOS" is_dyn_voltage="false" mode_sel_name="2E_MODE_SEL"/>
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<efxpt:iobank name="4A" iostd="1.8 V LVCMOS" is_dyn_voltage="false" mode_sel_name="4A_MODE_SEL"/>
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<efxpt:iobank name="4B" iostd="1.8 V LVCMOS" is_dyn_voltage="false" mode_sel_name="4B_MODE_SEL"/>
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<efxpt:iobank name="4C" iostd="1.8 V LVCMOS" is_dyn_voltage="false" mode_sel_name="4C_MODE_SEL"/>
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<efxpt:iobank name="4D" iostd="1.8 V LVCMOS" is_dyn_voltage="false" mode_sel_name="4D_MODE_SEL"/>
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<efxpt:iobank name="BL0" iostd="3.3 V LVCMOS" is_dyn_voltage="false" mode_sel_name="BL0_MODE_SEL"/>
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<efxpt:iobank name="BL1" iostd="3.3 V LVCMOS" is_dyn_voltage="false" mode_sel_name="BL1_MODE_SEL"/>
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<efxpt:iobank name="BL2" iostd="3.3 V LVCMOS" is_dyn_voltage="false" mode_sel_name="BL2_MODE_SEL"/>
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<efxpt:iobank name="BL3" iostd="3.3 V LVCMOS" is_dyn_voltage="false" mode_sel_name="BL3_MODE_SEL"/>
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<efxpt:iobank name="BR0" iostd="3.3 V LVCMOS" is_dyn_voltage="false" mode_sel_name="BR0_MODE_SEL"/>
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<efxpt:iobank name="BR1" iostd="3.3 V LVCMOS" is_dyn_voltage="false" mode_sel_name="BR1_MODE_SEL"/>
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<efxpt:iobank name="BR3" iostd="3.3 V LVCMOS" is_dyn_voltage="false" mode_sel_name="BR3_MODE_SEL"/>
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<efxpt:iobank name="BR4" iostd="3.3 V LVCMOS" is_dyn_voltage="false" mode_sel_name="BR4_MODE_SEL"/>
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<efxpt:iobank name="TL0" iostd="3.3 V LVCMOS" is_dyn_voltage="false" mode_sel_name="TL0_MODE_SEL"/>
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<efxpt:iobank name="TL1_TL5" iostd="3.3 V LVCMOS" is_dyn_voltage="false">
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<efxpt:mode_sel_name>
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<efxpt:pin_name bank_name="TL1" value="TL1_MODE_SEL"/>
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<efxpt:pin_name bank_name="TL5" value="TL5_MODE_SEL"/>
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</efxpt:mode_sel_name>
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</efxpt:iobank>
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<efxpt:iobank name="TR0" iostd="3.3 V LVCMOS" is_dyn_voltage="false" mode_sel_name="TR0_MODE_SEL"/>
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<efxpt:iobank name="TR1" iostd="3.3 V LVCMOS" is_dyn_voltage="false" mode_sel_name="TR1_MODE_SEL"/>
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<efxpt:iobank name="TR2" iostd="3.3 V LVCMOS" is_dyn_voltage="false" mode_sel_name="TR2_MODE_SEL"/>
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<efxpt:iobank name="TR3" iostd="3.3 V LVCMOS" is_dyn_voltage="false" mode_sel_name="TR3_MODE_SEL"/>
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<efxpt:iobank name="TR5" iostd="3.3 V LVCMOS" is_dyn_voltage="false" mode_sel_name="TR5_MODE_SEL"/>
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</efxpt:iobank_info>
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<efxpt:ctrl_info>
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<efxpt:ctrl name="cfg" ctrl_def="CONFIG_CTRL0" clock_name="" is_clk_invert="false" cbsel_bus_name="cfg_CBSEL" config_ctrl_name="cfg_CONFIG" ena_capture_name="cfg_ENA" error_status_name="cfg_ERROR" um_signal_status_name="cfg_USR_STATUS" is_remote_update_enable="false" is_user_mode_enable="false">
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<efxpt:gen_param>
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<efxpt:param name="remote_update_retries" value="0" value_type="int"/>
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</efxpt:gen_param>
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</efxpt:ctrl>
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</efxpt:ctrl_info>
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<efxpt:seu_info>
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<efxpt:seu name="seu" block_def="CONFIG_SEU0" mode="auto" ena_detect="false" wait_interval="16500000">
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<efxpt:gen_pin>
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<efxpt:pin name="seu_START" type_name="START" is_bus="false"/>
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<efxpt:pin name="seu_INJECT_ERROR" type_name="INJECT_ERROR" is_bus="false"/>
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<efxpt:pin name="seu_RST" type_name="RST" is_bus="false"/>
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<efxpt:pin name="seu_CONFIG" type_name="CONFIG" is_bus="false"/>
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<efxpt:pin name="seu_ERROR" type_name="ERROR" is_bus="false"/>
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<efxpt:pin name="seu_DONE" type_name="DONE" is_bus="false"/>
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</efxpt:gen_pin>
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</efxpt:seu>
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</efxpt:seu_info>
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<efxpt:clkmux_info>
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<efxpt:clkmux name="GCLKMUX_B" block_def="GCLKMUX_B" is_mux_bot0_dyn="false" is_mux_bot7_dyn="false">
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<efxpt:gen_pin>
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<efxpt:pin name="" type_name="ROUTE0" is_bus="false" is_clk="true" is_clk_invert="false"/>
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<efxpt:pin name="" type_name="ROUTE1" is_bus="false" is_clk="true" is_clk_invert="false"/>
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<efxpt:pin name="" type_name="ROUTE2" is_bus="false" is_clk="true" is_clk_invert="false"/>
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<efxpt:pin name="" type_name="ROUTE3" is_bus="false" is_clk="true" is_clk_invert="false"/>
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<efxpt:pin name="" type_name="DYN_MUX_OUT_0" is_bus="false"/>
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<efxpt:pin name="" type_name="DYN_MUX_OUT_7" is_bus="false"/>
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<efxpt:pin name="" type_name="DYN_MUX_SEL_0" is_bus="true"/>
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<efxpt:pin name="" type_name="DYN_MUX_SEL_7" is_bus="true"/>
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</efxpt:gen_pin>
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</efxpt:clkmux>
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<efxpt:clkmux name="GCLKMUX_L" block_def="GCLKMUX_L" is_mux_bot0_dyn="false" is_mux_bot7_dyn="false">
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<efxpt:gen_pin>
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<efxpt:pin name="" type_name="ROUTE0" is_bus="false" is_clk="true" is_clk_invert="false"/>
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<efxpt:pin name="" type_name="ROUTE1" is_bus="false" is_clk="true" is_clk_invert="false"/>
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<efxpt:pin name="" type_name="ROUTE2" is_bus="false" is_clk="true" is_clk_invert="false"/>
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<efxpt:pin name="" type_name="ROUTE3" is_bus="false" is_clk="true" is_clk_invert="false"/>
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<efxpt:pin name="" type_name="DYN_MUX_OUT_0" is_bus="false"/>
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<efxpt:pin name="" type_name="DYN_MUX_OUT_7" is_bus="false"/>
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<efxpt:pin name="" type_name="DYN_MUX_SEL_0" is_bus="true"/>
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<efxpt:pin name="" type_name="DYN_MUX_SEL_7" is_bus="true"/>
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</efxpt:gen_pin>
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</efxpt:clkmux>
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<efxpt:clkmux name="GCLKMUX_R" block_def="GCLKMUX_R" is_mux_bot0_dyn="false" is_mux_bot7_dyn="false">
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<efxpt:gen_pin>
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<efxpt:pin name="" type_name="ROUTE0" is_bus="false" is_clk="true" is_clk_invert="false"/>
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<efxpt:pin name="" type_name="ROUTE1" is_bus="false" is_clk="true" is_clk_invert="false"/>
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<efxpt:pin name="" type_name="ROUTE2" is_bus="false" is_clk="true" is_clk_invert="false"/>
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<efxpt:pin name="" type_name="ROUTE3" is_bus="false" is_clk="true" is_clk_invert="false"/>
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<efxpt:pin name="" type_name="DYN_MUX_OUT_0" is_bus="false"/>
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<efxpt:pin name="" type_name="DYN_MUX_OUT_7" is_bus="false"/>
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<efxpt:pin name="" type_name="DYN_MUX_SEL_0" is_bus="true"/>
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<efxpt:pin name="" type_name="DYN_MUX_SEL_7" is_bus="true"/>
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</efxpt:gen_pin>
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</efxpt:clkmux>
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<efxpt:clkmux name="GCLKMUX_T" block_def="GCLKMUX_T" is_mux_bot0_dyn="false" is_mux_bot7_dyn="false">
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<efxpt:gen_pin>
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<efxpt:pin name="" type_name="ROUTE0" is_bus="false" is_clk="true" is_clk_invert="false"/>
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<efxpt:pin name="" type_name="ROUTE1" is_bus="false" is_clk="true" is_clk_invert="false"/>
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<efxpt:pin name="" type_name="ROUTE2" is_bus="false" is_clk="true" is_clk_invert="false"/>
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<efxpt:pin name="" type_name="ROUTE3" is_bus="false" is_clk="true" is_clk_invert="false"/>
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<efxpt:pin name="" type_name="DYN_MUX_OUT_0" is_bus="false"/>
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<efxpt:pin name="" type_name="DYN_MUX_OUT_7" is_bus="false"/>
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<efxpt:pin name="" type_name="DYN_MUX_SEL_0" is_bus="true"/>
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<efxpt:pin name="" type_name="DYN_MUX_SEL_7" is_bus="true"/>
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</efxpt:gen_pin>
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</efxpt:clkmux>
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</efxpt:clkmux_info>
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</efxpt:device_info>
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<efxpt:gpio_info>
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<efxpt:global_unused_config state="input with weak pullup"/>
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</efxpt:gpio_info>
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<efxpt:pll_info/>
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<efxpt:osc_info/>
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<efxpt:lvds_info/>
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<efxpt:mipi_info/>
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<efxpt:jtag_info/>
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<efxpt:ddr_info/>
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<efxpt:mipi_dphy_info/>
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<efxpt:pll_ssc_info/>
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<efxpt:quad_lane_info/>
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<efxpt:quad_pcie_info/>
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<efxpt:lane_10g_info/>
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<efxpt:lane_1g_info/>
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<efxpt:raw_serdes_info/>
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<efxpt:soc_info/>
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</efxpt:design_db>
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@@ -0,0 +1,75 @@
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// do an entire round combinationally
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`define ROTL(x, n) {x[31-n:0], x[31:32-n]}
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module chacha20_qr #(
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parameter PIPELINE_STAGES=7
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)(
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input i_clk,
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input i_rst,
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input i_valid,
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output o_ready,
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input logic [31:0] a_i, b_i, c_i, d_i,
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output o_valid,
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input i_ready,
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output logic [31:0] a_o, b_o, c_o, d_o
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);
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logic [31:0] a_int [7];
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logic [31:0] b_int [7];
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logic [31:0] c_int [7];
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logic [31:0] d_int [7];
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logic [6:0] valid_sr;
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// There is an output stage which handles isolating backpressure from the rest
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// of the design from the core, so we don't need to worry about it here, we can
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// have a single signal gate all of this.
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assign o_ready = i_ready;
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always_ff @(posedge i_clk) begin
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if (i_rst) begin
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valid_sr <= '0;
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end else begin
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if (i_ready) begin
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// 1. Update A
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a_int[0] <= a_i + b_i;
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b_int[0] <= b_i;
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c_int[0] <= c_i;
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d_int[0] <= d_i;
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// 2. Update D
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a_int[1] <= a_int[0];
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b_int[1] <= b_int[0];
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c_int[1] <= c_int[0];
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d_int[1] <= `ROTL(a_int[0] ^ d_int[0], 16);
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end
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end
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end
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endmodule
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// always_comb begin
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// a_int_0 = a_i + b_i;
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// d_int_0 = a_int_0 ^ d_i;
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// d_int_1 = `ROTL(d_int_0, 16);
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// c_int_0 = c_i + d_int_1;
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// b_int_0 = c_int_0 ^ b_i;
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// b_int_1 = `ROTL(b_int_0, 12);
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// a_o = a_int_0 + b_int_1;
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// d_int_2 = d_int_1 ^ a_o;
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// d_o = `ROTL(d_int_2, 8);
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// c_o = c_int_0 + d_o;
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// b_int_2 = b_int_1 ^ c_o;
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// b_o = `ROTL(b_int_2, 7);
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// end
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// endmodule
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@@ -0,0 +1,107 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<efx:project name="chacha20_timing_test" description="" last_change="1751042439" sw_version="2025.1.110" last_run_state="pass" last_run_flow="syn" config_result_in_sync="true" design_ood="change" place_ood="change" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
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<efx:device_info>
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<efx:family name="Titanium"/>
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<efx:device name="Ti375N1156"/>
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<efx:timing_model name="C4"/>
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</efx:device_info>
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<efx:design_info def_veri_version="sv_09" def_vhdl_version="vhdl_2008" unified_flow="false">
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<efx:top_module name="chacha20_block"/>
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<efx:design_file name="../src/chacha20_qr.sv" version="default" library="default"/>
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<efx:design_file name="../src/chacha20_block.sv" version="default" library="default"/>
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<efx:top_vhdl_arch name=""/>
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</efx:design_info>
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<efx:constraint_info>
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<efx:sdc_file name="constraints.sdc"/>
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<efx:inter_file name=""/>
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</efx:constraint_info>
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<efx:sim_info/>
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<efx:misc_info/>
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<efx:ip_info/>
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<efx:synthesis tool_name="efx_map">
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<efx:param name="work_dir" value="work_syn" value_type="e_string"/>
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<efx:param name="write_efx_verilog" value="on" value_type="e_bool"/>
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<efx:param name="allow-const-ram-index" value="0" value_type="e_option"/>
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<efx:param name="blackbox-error" value="1" value_type="e_option"/>
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<efx:param name="blast_const_operand_adders" value="1" value_type="e_option"/>
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<efx:param name="bram_output_regs_packing" value="1" value_type="e_option"/>
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||||
<efx:param name="bram-push-tco-outreg" value="0" value_type="e_option"/>
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||||
<efx:param name="create-onehot-fsms" value="0" value_type="e_option"/>
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<efx:param name="fanout-limit" value="100" value_type="e_integer"/>
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||||
<efx:param name="hdl-compile-unit" value="1" value_type="e_option"/>
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||||
<efx:param name="hdl-loop-limit" value="20000" value_type="e_integer"/>
|
||||
<efx:param name="infer-clk-enable" value="3" value_type="e_option"/>
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||||
<efx:param name="infer-sync-set-reset" value="1" value_type="e_option"/>
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||||
<efx:param name="max_ram" value="-1" value_type="e_integer"/>
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||||
<efx:param name="max_mult" value="-1" value_type="e_integer"/>
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||||
<efx:param name="max-bit-blast-mem-size" value="10240" value_type="e_integer"/>
|
||||
<efx:param name="min-sr-fanout" value="0" value_type="e_integer"/>
|
||||
<efx:param name="min-ce-fanout" value="0" value_type="e_integer"/>
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||||
<efx:param name="mode" value="speed" value_type="e_option"/>
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||||
<efx:param name="mult-auto-pipeline" value="0" value_type="e_integer"/>
|
||||
<efx:param name="mult-decomp-retime" value="0" value_type="e_option"/>
|
||||
<efx:param name="operator-sharing" value="0" value_type="e_option"/>
|
||||
<efx:param name="optimize-adder-tree" value="0" value_type="e_option"/>
|
||||
<efx:param name="optimize-zero-init-rom" value="1" value_type="e_option"/>
|
||||
<efx:param name="peri-syn-instantiation" value="0" value_type="e_option"/>
|
||||
<efx:param name="peri-syn-inference" value="0" value_type="e_option"/>
|
||||
<efx:param name="ram-decomp-mode" value="0" value_type="e_option"/>
|
||||
<efx:param name="retiming" value="1" value_type="e_option"/>
|
||||
<efx:param name="seq_opt" value="1" value_type="e_option"/>
|
||||
<efx:param name="seq-opt-sync-only" value="0" value_type="e_option"/>
|
||||
<efx:param name="use-logic-for-small-mem" value="64" value_type="e_integer"/>
|
||||
<efx:param name="use-logic-for-small-rom" value="64" value_type="e_integer"/>
|
||||
<efx:param name="max_threads" value="-1" value_type="e_integer"/>
|
||||
<efx:param name="enable-mark-debug" value="1" value_type="e_option"/>
|
||||
<efx:param name="dsp-input-regs-packing" value="1" value_type="e_option"/>
|
||||
<efx:param name="dsp-output-regs-packing" value="1" value_type="e_option"/>
|
||||
<efx:param name="dsp-mac-packing" value="1" value_type="e_option"/>
|
||||
<efx:param name="insert-carry-skip" value="0" value_type="e_option"/>
|
||||
<efx:param name="pack-luts-to-comb4" value="0" value_type="e_option"/>
|
||||
</efx:synthesis>
|
||||
<efx:place_and_route tool_name="efx_pnr">
|
||||
<efx:param name="work_dir" value="work_pnr" value_type="e_string"/>
|
||||
<efx:param name="verbose" value="off" value_type="e_bool"/>
|
||||
<efx:param name="load_delaym" value="on" value_type="e_bool"/>
|
||||
<efx:param name="optimization_level" value="TIMING_3" value_type="e_option"/>
|
||||
<efx:param name="seed" value="3" value_type="e_integer"/>
|
||||
<efx:param name="placer_effort_level" value="5" value_type="e_option"/>
|
||||
<efx:param name="max_threads" value="-1" value_type="e_integer"/>
|
||||
<efx:param name="print_critical_path" value="10" value_type="e_integer"/>
|
||||
<efx:param name="classic_flow" value="off" value_type="e_noarg"/>
|
||||
<efx:param name="beneficial_skew" value="on" value_type="e_option"/>
|
||||
</efx:place_and_route>
|
||||
<efx:bitstream_generation tool_name="efx_pgm">
|
||||
<efx:param name="mode" value="active" value_type="e_option"/>
|
||||
<efx:param name="width" value="1" value_type="e_option"/>
|
||||
<efx:param name="enable_roms" value="smart" value_type="e_option"/>
|
||||
<efx:param name="spi_low_power_mode" value="on" value_type="e_bool"/>
|
||||
<efx:param name="io_weak_pullup" value="on" value_type="e_bool"/>
|
||||
<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option"/>
|
||||
<efx:param name="bitstream_compression" value="off" value_type="e_bool"/>
|
||||
<efx:param name="enable_external_master_clock" value="off" value_type="e_bool"/>
|
||||
<efx:param name="active_capture_clk_edge" value="negedge" value_type="e_option"/>
|
||||
<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string"/>
|
||||
<efx:param name="release_tri_then_reset" value="on" value_type="e_bool"/>
|
||||
<efx:param name="cold_boot" value="off" value_type="e_bool"/>
|
||||
<efx:param name="cascade" value="off" value_type="e_option"/>
|
||||
<efx:param name="generate_bit" value="on" value_type="e_bool"/>
|
||||
<efx:param name="generate_bitbin" value="off" value_type="e_bool"/>
|
||||
<efx:param name="generate_hex" value="on" value_type="e_bool"/>
|
||||
<efx:param name="generate_hexbin" value="off" value_type="e_bool"/>
|
||||
<efx:param name="four_byte_addressing" value="off" value_type="e_bool"/>
|
||||
</efx:bitstream_generation>
|
||||
<efx:debugger>
|
||||
<efx:param name="work_dir" value="work_dbg" value_type="e_string"/>
|
||||
<efx:param name="auto_instantiation" value="off" value_type="e_bool"/>
|
||||
<efx:param name="profile" value="NONE" value_type="e_string"/>
|
||||
</efx:debugger>
|
||||
<efx:security>
|
||||
<efx:param name="enable_bitstream_encrypt" value="off" value_type="e_bool"/>
|
||||
<efx:param name="enable_bitstream_auth" value="off" value_type="e_bool"/>
|
||||
<efx:param name="encryption_key_file" value="NONE" value_type="e_string"/>
|
||||
<efx:param name="auth_key_file" value="NONE" value_type="e_string"/>
|
||||
<efx:param name="randomize_iv_value" value="off" value_type="e_bool"/>
|
||||
<efx:param name="iv_value" value="" value_type="e_string"/>
|
||||
</efx:security>
|
||||
</efx:project>
|
||||
@@ -0,0 +1 @@
|
||||
create_clock -period 5.0 -name clk [get_ports i_clk]
|
||||
Reference in New Issue
Block a user