4 Commits

Author	SHA1	Message	Date
Byron Lathi	2b8286d180	Change target clock to 400MHz	2025-07-02 10:08:34 -07:00
Byron Lathi	196ea8e6d3	Add correct amount of memory ... should be 160, not 20. There are 8 cycles per stage and 20 stages	2025-06-29 13:29:38 -07:00
Byron Lathi	4c7badbbbb	Change target frequency to 250	2025-06-28 21:15:01 -07:00
Byron Lathi	8136a7526b	Add basic repo	2025-06-28 15:48:14 -07:00