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2fd1136154
Actually randomize testing
master
Byron Lathi
2025-10-27 20:13:21 -07:00
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06d5949aa7
Add rtl for friendly_modulo
Byron Lathi
2025-10-27 19:19:43 -07:00
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003527ee0d
Do poly1305 with absolutely no modulo operators
Byron Lathi
2025-10-26 16:09:16 -07:00
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fd50ecc4f0
Calculate r powers ahead of time
Byron Lathi
2025-10-26 15:43:58 -07:00
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faef39c4d3
Add modulo theory
Byron Lathi
2025-10-26 15:43:36 -07:00
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5e3b7be854
Add parallel implementation
Byron Lathi
2025-10-24 18:46:30 -07:00
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d9651e9074
Add poly1305 python implementation
Byron Lathi
2025-10-24 08:25:35 -07:00
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80e3faeae6
ramblings
Byron Lathi
2025-07-14 11:10:43 -07:00
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2b57079205
Add poly1305 and synthesis test
Byron Lathi
2025-07-05 07:30:18 -07:00
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7f91a8af32
Get poly1305 core to kind of work
Byron Lathi
2025-07-04 10:49:48 -07:00
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2b8286d180
Change target clock to 400MHz
Byron Lathi
2025-07-02 10:08:25 -07:00
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548bee1144
Add taxi
Byron Lathi
2025-07-02 10:08:10 -07:00
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2afe869dee
Add missing ready, fix constant endianness
Byron Lathi
2025-07-02 09:39:55 -07:00
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a617277005
First shot at 1/4 version
Byron Lathi
2025-07-02 06:32:58 -07:00
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196ea8e6d3
Add correct amount of memory
Byron Lathi
2025-06-29 13:29:38 -07:00
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4c7badbbbb
Change target frequency to 250
Byron Lathi
2025-06-28 21:15:01 -07:00
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20d98e117b
Get sim working, make some changes to the final addition
Byron Lathi
2025-06-28 20:34:46 -07:00
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8136a7526b
Add basic repo
Byron Lathi
2025-06-28 15:48:14 -07:00
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369e29557c
add notes
Byron Lathi
2025-06-23 00:02:14 -07:00
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4b67e7aa5a
Initial Commit
Byron Lathi
2025-06-22 21:43:49 -07:00