Byron Lathi
cedec1ed1f
I highly doubt this will pass timing... need to make a test harness to synthesize
27 lines
646 B
Markdown
27 lines
646 B
Markdown
# Requirements
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* 2 Gbps operation
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* Handles both encrypt and decrypt
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At reasonable FPGA speed of 250MHz, 2 Gbps requires a minimum width of 8 bits.
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32 bits is a reasonable data width that would be common to see, and lets us
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have more breathing room while still maintaining line rate.
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Module inputs and outputs
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* clk
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* rst
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* data_in [31:0]
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* data_valid
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* data_ready
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* data_last
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* r [127:0]
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* s [127:0]
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* mac [127:0]
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* mac_valid
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There is no output backpressure. since the result is just a single 128 bit number,
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we don't need to have a ready signal. if you want to add backpressure, add a register
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slice on the output outside of this module.
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