drivers: add dma spinal dmesg driver
Signed-off-by: Dolu1990 <charles.papon.90@gmail.com> Signed-off-by: Mohamad Noor Alim Hussin <mnalim@efinixinc.com>
This commit is contained in:
Mohamad Noor Alim Hussin
@@ -570,6 +570,12 @@ config STM32_MDMA
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If you have a board based on STM32 SoC and wish to use the master DMA
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say Y here.
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config SPINAL_LIB_DMASG
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tristate "SpinalHDL lib DMASG"
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select DMA_ENGINE
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help
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Enable support for SpinalHDL lib DMASG controller.
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config SPRD_DMA
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tristate "Spreadtrum DMA support"
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depends on ARCH_SPRD || COMPILE_TEST
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@@ -70,6 +70,7 @@ obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
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obj-$(CONFIG_STM32_DMA) += stm32-dma.o
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obj-$(CONFIG_STM32_DMAMUX) += stm32-dmamux.o
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obj-$(CONFIG_STM32_MDMA) += stm32-mdma.o
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obj-$(CONFIG_SPINAL_LIB_DMASG) += spinal-lib-dmasg.o
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obj-$(CONFIG_SPRD_DMA) += sprd-dma.o
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obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o
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obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
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768
drivers/dma/spinal-lib-dmasg.c
Normal file
768
drivers/dma/spinal-lib-dmasg.c
Normal file
@@ -0,0 +1,768 @@
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#include <linux/bitops.h>
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#include <linux/dmapool.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_dma.h>
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#include <linux/of_platform.h>
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#include <linux/of_irq.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include "dmaengine.h"
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#pragma GCC diagnostic ignored "-Wunused-function"
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#define write_u32(data, address) writel(data,address)
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#define read_u32(address) readl(address)
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#define BIT_0 (1 << 0)
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#define BIT_1 (1 << 1)
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#define BIT_2 (1 << 2)
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#define BIT_3 (1 << 3)
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#define BIT_4 (1 << 4)
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#define BIT_5 (1 << 5)
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#define BIT_6 (1 << 6)
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#define BIT_7 (1 << 7)
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#define BIT_8 (1 << 8)
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#define BIT_9 (1 << 9)
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#define BIT_10 (1 << 10)
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#define BIT_11 (1 << 11)
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#define BIT_12 (1 << 12)
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#define BIT_13 (1 << 13)
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#define BIT_14 (1 << 14)
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#define BIT_15 (1 << 15)
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#define BIT_16 (1 << 16)
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#define BIT_17 (1 << 17)
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#define BIT_18 (1 << 18)
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#define BIT_19 (1 << 19)
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#define BIT_20 (1 << 20)
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#define BIT_21 (1 << 21)
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#define BIT_22 (1 << 22)
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#define BIT_23 (1 << 23)
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#define BIT_24 (1 << 24)
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#define BIT_25 (1 << 25)
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#define BIT_26 (1 << 26)
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#define BIT_27 (1 << 27)
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#define BIT_28 (1 << 28)
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#define BIT_29 (1 << 29)
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#define BIT_30 (1 << 30)
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#define BIT_31 (1 << 31)
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#define dmasg_ca (base + channel*0x80)
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#define DMASG_CHANNEL_INPUT_ADDRESS 0x00
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#define DMASG_CHANNEL_INPUT_STREAM 0x08
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#define DMASG_CHANNEL_INPUT_CONFIG 0x0C
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#define DMASG_CHANNEL_INPUT_CONFIG_MEMORY BIT_12
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#define DMASG_CHANNEL_INPUT_CONFIG_STREAM 0
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#define DMASG_CHANNEL_INPUT_CONFIG_COMPLETION_ON_PACKET BIT_13
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#define DMASG_CHANNEL_INPUT_CONFIG_WAIT_ON_PACKET BIT_14
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#define DMASG_CHANNEL_OUTPUT_ADDRESS 0x10
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#define DMASG_CHANNEL_OUTPUT_STREAM 0x18
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#define DMASG_CHANNEL_OUTPUT_CONFIG 0x1C
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#define DMASG_CHANNEL_OUTPUT_CONFIG_MEMORY BIT_12
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#define DMASG_CHANNEL_OUTPUT_CONFIG_STREAM 0
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#define DMASG_CHANNEL_OUTPUT_CONFIG_LAST BIT_13
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#define DMASG_CHANNEL_DIRECT_BYTES 0x20
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#define DMASG_CHANNEL_STATUS 0x2C
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#define DMASG_CHANNEL_STATUS_DIRECT_START BIT_0
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#define DMASG_CHANNEL_STATUS_BUSY BIT_0
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#define DMASG_CHANNEL_STATUS_SELF_RESTART BIT_1
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#define DMASG_CHANNEL_STATUS_STOP BIT_2
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#define DMASG_CHANNEL_STATUS_LINKED_LIST_START BIT_4
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#define DMASG_CHANNEL_FIFO 0x40
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#define DMASG_CHANNEL_PRIORITY 0x44
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#define DMASG_CHANNEL_INTERRUPT_ENABLE 0x50
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#define DMASG_CHANNEL_INTERRUPT_PENDING 0x54
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// Interrupt at the end of each descriptor
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#define DMASG_CHANNEL_INTERRUPT_DESCRIPTOR_COMPLETION_MASK BIT_0
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// Interrupt at the middle of each descriptor, require the half_completion_interrupt option to be enabled for the channel
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#define DMASG_CHANNEL_INTERRUPT_DESCRIPTOR_COMPLETION_HALF_MASK BIT_1
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// Interrupt when the channel is going off (not busy anymore)
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#define DMASG_CHANNEL_INTERRUPT_CHANNEL_COMPLETION_MASK BIT_2
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// Interrupt each time that a linked list's descriptor status field is updated
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#define DMASG_CHANNEL_INTERRUPT_LINKED_LIST_UPDATE_MASK BIT_3
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// Interrupt each time a S -> M channel has done transferring a packet into the memory
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#define DMASG_CHANNEL_INTERRUPT_INPUT_PACKET_MASK BIT_4
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#define DMASG_CHANNEL_PROGRESS_BYTES 0x60
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#define DMASG_CHANNEL_LINKED_LIST_HEAD 0x70
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// Number of bytes (minus one) reserved at the descriptor FROM/TO addresses.
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// If you want to transfer 10 bytes, this field should take the value 9
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#define DMASG_DESCRIPTOR_CONTROL_BYTES 0x7FFFFFF
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//Only for M -> S transfers, specify if a end of packet should be send at the end of the transfer
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#define DMASG_DESCRIPTOR_CONTROL_END_OF_PACKET BIT_30
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// Number of bytes transferred by the DMA for this descriptor.
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#define DMASG_DESCRIPTOR_STATUS_BYTES 0x7FFFFFF
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// Only for S -> M transfers, specify if the descriptor mark the end of a received packet
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// Can be used when the dmasg_input_stream function is called with completion_on_packet set.
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#define DMASG_DESCRIPTOR_STATUS_END_OF_PACKET BIT_30
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// Specify if the descriptor was executed by the DMA.
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// If the DMA read a completed descriptor, the channel is stopped and will produce a CHANNEL_COMPLETION interrupt.
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#define DMASG_DESCRIPTOR_STATUS_COMPLETED BIT_31
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// byte_per_burst need to be a power of two, can be set to zero if the channel has hardcoded burst length
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static void dmasg_input_memory(void __iomem * base, u32 channel, u32 address, u32 byte_per_burst){
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write_u32(address, dmasg_ca + DMASG_CHANNEL_INPUT_ADDRESS);
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write_u32(DMASG_CHANNEL_INPUT_CONFIG_MEMORY | ((byte_per_burst-1) & 0xFFF), dmasg_ca + DMASG_CHANNEL_INPUT_CONFIG);
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}
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// byte_per_burst need to be a power of two, can be set to zero if the channel has hardcoded burst length
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static void dmasg_output_memory(void __iomem * base, u32 channel, u32 address, u32 byte_per_burst){
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write_u32(address, dmasg_ca + DMASG_CHANNEL_OUTPUT_ADDRESS);
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write_u32(DMASG_CHANNEL_OUTPUT_CONFIG_MEMORY | ((byte_per_burst-1) & 0xFFF), dmasg_ca + DMASG_CHANNEL_OUTPUT_CONFIG);
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}
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// port identify which physical input port should be used. ex : If a port can be accessed by 4 channels, and you are the second of those channel, then port=1
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// wait_on_packet ensure the channel wait the beggining of a packet before capturing the data (avoid desync)
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// completion_on_packet will limit the descriptor to only contains one packet and force its completion when it is fully transferred into memory.
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static void dmasg_input_stream(void __iomem * base, u32 channel, u32 port, u32 wait_on_packet, u32 completion_on_packet){
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write_u32(port << 0, dmasg_ca + DMASG_CHANNEL_INPUT_STREAM);
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write_u32(DMASG_CHANNEL_INPUT_CONFIG_STREAM | (completion_on_packet ? DMASG_CHANNEL_INPUT_CONFIG_COMPLETION_ON_PACKET : 0) | (wait_on_packet ? DMASG_CHANNEL_INPUT_CONFIG_WAIT_ON_PACKET : 0), dmasg_ca + DMASG_CHANNEL_INPUT_CONFIG);
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}
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// port identify which physical output port should be used. ex : If a port can be accessed by 4 channels, and you are the second of those channel, then port=1
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// source is equivalent to the AXI-Stream TID used in the packet
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// sink is equivalent to the AXI-Stream TDEST used in the packet
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// last (only for direct DMA control, not linked list) specify if a end of packet should be sent at the end of the transfer
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static void dmasg_output_stream(void __iomem * base, u32 channel, u32 port, u32 source, u32 sink, u32 last){
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write_u32(port << 0 | source << 8 | sink << 16, dmasg_ca + DMASG_CHANNEL_OUTPUT_STREAM);
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write_u32(DMASG_CHANNEL_OUTPUT_CONFIG_STREAM | (last ? DMASG_CHANNEL_OUTPUT_CONFIG_LAST : 0), dmasg_ca + DMASG_CHANNEL_OUTPUT_CONFIG);
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}
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// Allow to start a channel without using linked list (direct control). Be sure the channel was enabled to support this mode.
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// channel is the DMA channel ID to use.
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// bytes is the size of the transfer
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// self_restart allow the channel to operate into a circular mode. The DESCRIPTOR_COMPLETION_HALF interrupt can be usefull in that mode
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static void dmasg_direct_start(void __iomem * base, u32 channel, u32 bytes, u32 self_restart){
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write_u32(bytes-1, dmasg_ca + DMASG_CHANNEL_DIRECT_BYTES);
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write_u32(DMASG_CHANNEL_STATUS_DIRECT_START | (self_restart ? DMASG_CHANNEL_STATUS_SELF_RESTART : 0), dmasg_ca + DMASG_CHANNEL_STATUS);
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}
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// Allow to start a channel using a linked list. Be sure the channel was enabled to support this mode.
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// channel is the DMA channel ID to use.
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// head specify the address of the linked list's first element. See dmasg_descriptor struct.
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static void dmasg_linked_list_start(void __iomem * base, u32 channel, u32 head){
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write_u32((u32) head, dmasg_ca + DMASG_CHANNEL_LINKED_LIST_HEAD);
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write_u32(DMASG_CHANNEL_STATUS_LINKED_LIST_START, dmasg_ca + DMASG_CHANNEL_STATUS);
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}
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// Ask a channel to stop itself. None blocking, so you need to pull on dmasg_busy if you want to wait it to be effective.
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// The status progress (bytes transfered) of the interrupted descriptor will be unknown
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static void dmasg_stop(void __iomem * base, u32 channel){
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write_u32(DMASG_CHANNEL_STATUS_STOP, dmasg_ca + DMASG_CHANNEL_STATUS);
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}
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// See all DMASG_CHANNEL_INTERRUPT_*_MASK defines for possible interrupts
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// Multiple interrupts can be used at once
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// This function clear all pending interrupts for the given channel before enabling the mask's interrupts
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static void dmasg_interrupt_config(void __iomem * base, u32 channel, u32 mask){
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write_u32(0xFFFFFFFF, dmasg_ca+DMASG_CHANNEL_INTERRUPT_PENDING);
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write_u32(mask, dmasg_ca+DMASG_CHANNEL_INTERRUPT_ENABLE);
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}
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// clear the mask's interrupts, you can mask with 0xFFFFFFFF to clear them all
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static void dmasg_interrupt_pending_clear(void __iomem * base, u32 channel, u32 mask){
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write_u32(mask, dmasg_ca+DMASG_CHANNEL_INTERRUPT_PENDING);
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}
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// Check the status of the specified channel.
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static u32 dmasg_busy(void __iomem * base, u32 channel){
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return read_u32(dmasg_ca + DMASG_CHANNEL_STATUS) & DMASG_CHANNEL_STATUS_BUSY;
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}
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// Specify the buffer mapping of the given channel
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// You don't need to use this function is the buffer address and buffer size are hardcoded in the hardware
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static void dmasg_buffer(void __iomem * base, u32 channel, u32 fifo_base, u32 fifo_bytes){
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write_u32(fifo_base << 0 | (fifo_bytes-1) << 16, dmasg_ca+DMASG_CHANNEL_FIFO);
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}
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static void dmasg_priority(void __iomem * base, u32 channel, u32 priority){
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write_u32(priority, dmasg_ca + DMASG_CHANNEL_PRIORITY);
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}
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// Snoop how many bytes were transferred for the current descriptor
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static u32 dmasg_progress_bytes(void __iomem * base, u32 channel){
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return read_u32(dmasg_ca + DMASG_CHANNEL_PROGRESS_BYTES);
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}
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#define SPINAL_LIB_DMASG_MAX_TRANS_LEN (1 << 24)
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struct spinal_lib_dmasg_chan {
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struct spinal_lib_dmasg_device *priv;
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struct device *dev;
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int hardware_id;
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int software_id;
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spinlock_t lock;
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struct dma_chan common;
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struct dma_pool *segment_pool;
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struct list_head pending_list;
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struct spinal_lib_dmasg_tx_descriptor *current_descriptor;
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struct spinal_lib_dmasg_segment * current_segment;
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int irq;
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struct tasklet_struct tasklet;
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};
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struct spinal_lib_dmasg_device {
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void __iomem *regs;
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struct device *dev;
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struct dma_device common;
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int chan_count;
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struct spinal_lib_dmasg_chan *chan;
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};
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#define to_spinal_lib_dmasg_chan(chan) \
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container_of(chan, struct spinal_lib_dmasg_chan, common)
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#define to_dma_tx_descriptor(tx) \
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container_of(tx, struct spinal_lib_dmasg_tx_descriptor, async_tx)
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struct spinal_lib_dmasg_tx_descriptor {
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struct dma_async_tx_descriptor async_tx;
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struct list_head segments;
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struct list_head node;
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u32 period_left, period_len;
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u32 buffer_left, buffer_len;
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dma_addr_t buf_addr;
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};
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struct spinal_lib_dmasg_segment_hw {
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u32 status;
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u32 control;
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u64 from;
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u64 to;
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u64 next;
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} __aligned(64);
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/**
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*
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*/
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struct spinal_lib_dmasg_segment {
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struct spinal_lib_dmasg_segment_hw hw;
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struct list_head node;
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struct spinal_lib_dmasg_segment* next;
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dma_addr_t phys;
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bool notify;
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} __aligned(64);
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static struct spinal_lib_dmasg_segment *spinal_lib_dmasg_alloc_segment(struct spinal_lib_dmasg_chan *chan)
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{
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struct spinal_lib_dmasg_segment *segment;
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dma_addr_t phys;
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segment = dma_pool_zalloc(chan->segment_pool, GFP_ATOMIC, &phys);
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if (!segment)
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return NULL;
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segment->phys = phys;
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return segment;
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}
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static struct spinal_lib_dmasg_tx_descriptor *
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spinal_lib_dmasg_alloc_tx_descriptor(struct spinal_lib_dmasg_chan *chan)
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{
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struct spinal_lib_dmasg_tx_descriptor *desc;
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desc = kzalloc(sizeof(*desc), GFP_KERNEL);
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if (!desc)
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return NULL;
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INIT_LIST_HEAD(&desc->segments);
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return desc;
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}
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static int spinal_lib_dmasg_free_tx_descriptor(struct spinal_lib_dmasg_chan *chan, struct spinal_lib_dmasg_tx_descriptor *desc){
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struct spinal_lib_dmasg_segment *segment;
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//printk("spinal_lib_dmasg_free_tx_descriptor %x %x %x\n", (u32)&(desc->segments), (u32)(desc->segments.prev), (u32)(desc->segments.next));
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list_for_each_entry(segment, &desc->segments, node) {
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dma_pool_free(chan->segment_pool, segment, segment->phys);
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}
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kzfree(desc);
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return 0;
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}
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static int spinal_lib_dmasg_chan_reset(struct spinal_lib_dmasg_chan *chan)
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{
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//printk("spinal_lib_dmasg_chan_reset\n");
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return 0;
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}
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static void spinal_lib_dmasg_cyclic_segment_update(struct spinal_lib_dmasg_chan* chan, bool init){
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unsigned long flags = 0;
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if(!init)
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spin_lock_irqsave(&chan->lock, flags);
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// printk("spinal_lib_dmasg_cyclic_segment_update\n");
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while(1){
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dma_async_tx_callback callback;
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void *callback_param;
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struct spinal_lib_dmasg_segment *segment;
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struct spinal_lib_dmasg_tx_descriptor *desc;
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u32 bytes;
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segment = chan->current_segment;
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desc = chan->current_descriptor;
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if(!segment || !(segment->hw.status & DMASG_DESCRIPTOR_STATUS_COMPLETED)) {
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break;
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}
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if(!init && segment->notify){
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callback = desc->async_tx.callback;
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callback_param = desc->async_tx.callback_param;
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} else {
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callback = NULL;
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}
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// Update segment
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bytes = min_t(u32, min_t(u32, SPINAL_LIB_DMASG_MAX_TRANS_LEN, desc->period_left), desc->buffer_left);
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segment->hw.control = bytes-1;
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segment->hw.from = desc->buf_addr + (desc->buffer_len - desc->buffer_left);
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segment->hw.status = 0;
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// Update for next desc
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desc->period_left -= bytes;
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desc->buffer_left -= bytes;
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if(desc->period_left == 0){
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desc->period_left = desc->period_len;
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segment->notify = true;
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} else {
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segment->notify = false;
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}
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if(desc->buffer_left == 0){
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desc->buffer_left = desc->buffer_len;
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}
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chan->current_segment = segment->next;
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if(callback){
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spin_unlock_irqrestore(&chan->lock, flags);
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callback(callback_param);
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spin_lock_irqsave(&chan->lock, flags);
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}
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}
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if(!init)
|
||||
spin_unlock_irqrestore(&chan->lock, flags);
|
||||
}
|
||||
|
||||
static void spinal_lib_dmasg_do_tasklet(unsigned long data)
|
||||
{
|
||||
struct spinal_lib_dmasg_chan *chan = (struct spinal_lib_dmasg_chan *)data;
|
||||
|
||||
//printk("spinal_lib_dmasg_do_tasklet %x\n", (u32)chan);
|
||||
|
||||
|
||||
spinal_lib_dmasg_cyclic_segment_update(chan, false);
|
||||
|
||||
}
|
||||
|
||||
static irqreturn_t spinal_lib_dmasg_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct spinal_lib_dmasg_chan *chan = dev_id;
|
||||
|
||||
//printk("spinal_lib_dmasg_interrupt %d %p\n", irq, dev_id);
|
||||
|
||||
|
||||
|
||||
dmasg_interrupt_config(chan->priv->regs, chan->hardware_id, DMASG_CHANNEL_INTERRUPT_DESCRIPTOR_COMPLETION_MASK);
|
||||
|
||||
|
||||
tasklet_schedule(&chan->tasklet);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int spinal_lib_dmasg_chan_probe(struct spinal_lib_dmasg_device *priv,
|
||||
struct device_node *node, int software_id)
|
||||
{
|
||||
struct spinal_lib_dmasg_chan *chan;
|
||||
int err;
|
||||
|
||||
//printk("spinal_lib_dmasg_chan_probe enter\n");
|
||||
|
||||
chan = &priv->chan[software_id];
|
||||
chan->dev = priv->dev;
|
||||
chan->priv = priv;
|
||||
chan->software_id = software_id;
|
||||
|
||||
|
||||
spin_lock_init(&chan->lock);
|
||||
INIT_LIST_HEAD(&chan->pending_list);
|
||||
chan->segment_pool = dma_pool_create("spinal_lib_dmasg_segment_pool",
|
||||
chan->dev,
|
||||
sizeof(struct spinal_lib_dmasg_segment),
|
||||
__alignof__(struct spinal_lib_dmasg_segment),
|
||||
0);
|
||||
|
||||
/* Retrieve the channel properties from the device tree */
|
||||
err = of_property_read_s32(node, "reg", &chan->hardware_id );
|
||||
if (err) {
|
||||
dev_err(priv->dev, "missing hardware-id property\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Initialize the DMA channel and add it to the DMA engine channels
|
||||
* list.
|
||||
*/
|
||||
chan->common.device = &priv->common;
|
||||
|
||||
list_add_tail(&chan->common.device_node, &priv->common.channels);
|
||||
|
||||
/* Reset the channel */
|
||||
err = spinal_lib_dmasg_chan_reset(chan);
|
||||
if (err < 0) {
|
||||
dev_err(priv->dev, "Reset channel failed\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
/* Initialize the tasklet */
|
||||
tasklet_init(&chan->tasklet, spinal_lib_dmasg_do_tasklet, (unsigned long)chan);
|
||||
|
||||
/* Request the interrupt */
|
||||
chan->irq = irq_of_parse_and_map(node, 0);
|
||||
err = request_irq(chan->irq, spinal_lib_dmasg_interrupt, IRQF_SHARED,
|
||||
"spinal-lib-dmasg", chan);
|
||||
if (err) {
|
||||
dev_err(chan->dev, "unable to request IRQ %d\n", chan->irq);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spinal_lib_dmasg_alloc_chan_resources(struct dma_chan *dchan)
|
||||
{
|
||||
//printk("spinal_lib_dmasg_alloc_chan_resources\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void spinal_lib_dmasg_free_chan_resources(struct dma_chan *dchan)
|
||||
{
|
||||
//printk("spinal_lib_dmasg_free_chan_resources\n");
|
||||
|
||||
}
|
||||
|
||||
|
||||
static int spinal_lib_dmasg_terminate_all(struct dma_chan *dchan)
|
||||
{
|
||||
struct spinal_lib_dmasg_chan *chan = to_spinal_lib_dmasg_chan(dchan);
|
||||
struct spinal_lib_dmasg_tx_descriptor *desc;
|
||||
unsigned long flags;
|
||||
//printk("spinal_lib_dmasg_terminate_all\n");
|
||||
|
||||
spin_lock_irqsave(&chan->lock, flags);
|
||||
|
||||
dmasg_interrupt_config(chan->priv->regs, chan->hardware_id, 0);
|
||||
dmasg_stop(chan->priv->regs, chan->hardware_id);
|
||||
while(dmasg_busy(chan->priv->regs, chan->hardware_id));
|
||||
|
||||
|
||||
if(chan->current_descriptor){
|
||||
spinal_lib_dmasg_free_tx_descriptor(chan, chan->current_descriptor);
|
||||
chan->current_descriptor = NULL;
|
||||
chan->current_segment = NULL;
|
||||
}
|
||||
|
||||
list_for_each_entry(desc, &chan->pending_list, node) {
|
||||
spinal_lib_dmasg_free_tx_descriptor(chan, desc);
|
||||
}
|
||||
|
||||
INIT_LIST_HEAD(&chan->pending_list);
|
||||
spin_unlock_irqrestore(&chan->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
static void spinal_lib_dmasg_issue_pending(struct dma_chan *dchan)
|
||||
{
|
||||
struct spinal_lib_dmasg_chan *chan = to_spinal_lib_dmasg_chan(dchan);
|
||||
struct spinal_lib_dmasg_tx_descriptor *desc;
|
||||
struct spinal_lib_dmasg_segment * head_segment;
|
||||
unsigned long flags;
|
||||
//printk("spinal_lib_dmasg_issue_pending\n");
|
||||
|
||||
spin_lock_irqsave(&chan->lock, flags);
|
||||
|
||||
if (list_empty(&chan->pending_list))
|
||||
goto done;
|
||||
|
||||
desc = list_first_entry(&chan->pending_list, struct spinal_lib_dmasg_tx_descriptor, node);
|
||||
head_segment = list_first_entry(&desc->segments, struct spinal_lib_dmasg_segment, node);
|
||||
|
||||
list_del_init(&desc->node);
|
||||
|
||||
chan->current_descriptor = desc;
|
||||
chan->current_segment = head_segment;
|
||||
|
||||
spinal_lib_dmasg_cyclic_segment_update(chan, true);
|
||||
|
||||
dmasg_interrupt_config(chan->priv->regs, chan->hardware_id, DMASG_CHANNEL_INTERRUPT_DESCRIPTOR_COMPLETION_MASK);
|
||||
dmasg_input_memory(chan->priv->regs, chan->hardware_id, 0, 16);
|
||||
dmasg_output_stream (chan->priv->regs, chan->hardware_id, 0, 0, 0, 1);
|
||||
dmasg_linked_list_start(chan->priv->regs, chan->hardware_id, (u32) head_segment->phys);
|
||||
|
||||
|
||||
|
||||
done:
|
||||
spin_unlock_irqrestore(&chan->lock, flags);
|
||||
}
|
||||
|
||||
static enum dma_status spinal_lib_dmasg_tx_status(struct dma_chan *dchan,
|
||||
dma_cookie_t cookie,
|
||||
struct dma_tx_state *txstate)
|
||||
{
|
||||
//printk("spinal_lib_dmasg_tx_status\n");
|
||||
return DMA_IN_PROGRESS;
|
||||
}
|
||||
|
||||
static struct dma_chan *of_dma_spinal_lib_xlate(struct of_phandle_args *dma_spec,
|
||||
struct of_dma *ofdma)
|
||||
{
|
||||
struct spinal_lib_dmasg_device *priv = ofdma->of_dma_data;
|
||||
int chan_id;
|
||||
|
||||
//printk("of_dma_spinal_lib_xlate !!!!!\n");
|
||||
chan_id = dma_spec->args[0];
|
||||
if (chan_id >= priv->chan_count)
|
||||
return NULL;
|
||||
|
||||
return dma_get_slave_channel(&priv->chan[chan_id].common); // dma_get_slave_channel(&priv->chan[chan_id]->common);
|
||||
}
|
||||
|
||||
|
||||
static dma_cookie_t spinal_lib_dmasg_tx_submit(struct dma_async_tx_descriptor *tx)
|
||||
{
|
||||
struct spinal_lib_dmasg_tx_descriptor *desc = to_dma_tx_descriptor(tx);
|
||||
struct spinal_lib_dmasg_chan *chan = to_spinal_lib_dmasg_chan(tx->chan);
|
||||
dma_cookie_t cookie;
|
||||
unsigned long flags;
|
||||
|
||||
//printk("spinal_lib_dmasg_tx_submit\n");
|
||||
|
||||
spin_lock_irqsave(&chan->lock, flags);
|
||||
|
||||
cookie = dma_cookie_assign(tx);
|
||||
list_add_tail(&desc->node, &chan->pending_list);
|
||||
|
||||
spin_unlock_irqrestore(&chan->lock, flags);
|
||||
|
||||
return cookie;
|
||||
}
|
||||
|
||||
|
||||
static struct dma_async_tx_descriptor *spinal_lib_dmasg_prep_dma_cyclic(
|
||||
struct dma_chan *dchan, dma_addr_t buf_addr, size_t buf_len,
|
||||
size_t period_len, enum dma_transfer_direction direction,
|
||||
unsigned long flags)
|
||||
{
|
||||
struct spinal_lib_dmasg_chan *chan = to_spinal_lib_dmasg_chan(dchan);
|
||||
struct spinal_lib_dmasg_tx_descriptor * desc;
|
||||
struct spinal_lib_dmasg_segment *head_segment, *prev = NULL;
|
||||
int i;
|
||||
|
||||
//printk("spinal_lib_dmasg_prep_dma_cyclic\n");
|
||||
|
||||
if (!period_len)
|
||||
return NULL;
|
||||
|
||||
desc = spinal_lib_dmasg_alloc_tx_descriptor(chan);
|
||||
|
||||
dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
|
||||
desc->async_tx.tx_submit = spinal_lib_dmasg_tx_submit;
|
||||
desc->period_len = period_len;
|
||||
desc->period_left = period_len;
|
||||
desc->buffer_len = buf_len;
|
||||
desc->buffer_left = buf_len;
|
||||
desc->buf_addr = buf_addr;
|
||||
|
||||
for (i = 0; i < 10; ++i) {
|
||||
struct spinal_lib_dmasg_segment *segment;
|
||||
|
||||
segment = spinal_lib_dmasg_alloc_segment(chan);
|
||||
segment->hw.status = DMASG_DESCRIPTOR_STATUS_COMPLETED;
|
||||
|
||||
if (prev){
|
||||
prev->hw.next = segment->phys;
|
||||
prev->next = segment;
|
||||
}
|
||||
|
||||
prev = segment;
|
||||
|
||||
list_add_tail(&segment->node, &desc->segments);
|
||||
}
|
||||
|
||||
head_segment = list_first_entry(&desc->segments, struct spinal_lib_dmasg_segment, node);
|
||||
prev->hw.next = head_segment->phys;
|
||||
prev->next = head_segment;
|
||||
|
||||
return &desc->async_tx;
|
||||
}
|
||||
|
||||
static struct dma_async_tx_descriptor *spinal_lib_dmasg_prep_slave_sg(
|
||||
struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
|
||||
enum dma_transfer_direction direction, unsigned long flags,
|
||||
void *context)
|
||||
{
|
||||
//printk("spinal_lib_dmasg_prep_slave_sg\n");
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void spinal_lib_dmasg_chan_remove(struct spinal_lib_dmasg_chan *chan)
|
||||
{
|
||||
//printk("spinal_lib_dmasg_chan_remove\n");
|
||||
|
||||
list_del(&chan->common.device_node);
|
||||
}
|
||||
|
||||
static int spinal_lib_dmasg_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spinal_lib_dmasg_device *priv;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct device_node *child = pdev->dev.of_node;
|
||||
int i, err;
|
||||
|
||||
//printk("spinal_lib_dmasg_probe\n");
|
||||
|
||||
/* Allocate and initialize the DMA engine structure */
|
||||
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
|
||||
priv->dev = &pdev->dev;
|
||||
priv->common.dev = &pdev->dev;
|
||||
|
||||
/* Count sub channels */
|
||||
priv->chan_count = 0;
|
||||
for_each_child_of_node(node, child) {
|
||||
priv->chan_count += 1;
|
||||
}
|
||||
|
||||
priv->chan = devm_kzalloc(&pdev->dev, sizeof(*priv->chan)*priv->chan_count, GFP_KERNEL);
|
||||
if (!priv->chan)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Request and map I/O memory */
|
||||
priv->regs = devm_ioremap_resource(&pdev->dev, platform_get_resource(pdev, IORESOURCE_MEM, 0));
|
||||
if (IS_ERR(priv->regs))
|
||||
return PTR_ERR(priv->regs);
|
||||
|
||||
INIT_LIST_HEAD(&priv->common.channels);
|
||||
dma_cap_set(DMA_CYCLIC, priv->common.cap_mask);
|
||||
|
||||
priv->common.device_prep_slave_sg = spinal_lib_dmasg_prep_slave_sg;
|
||||
priv->common.device_alloc_chan_resources = spinal_lib_dmasg_alloc_chan_resources;
|
||||
priv->common.device_free_chan_resources = spinal_lib_dmasg_free_chan_resources;
|
||||
priv->common.device_terminate_all = spinal_lib_dmasg_terminate_all;
|
||||
priv->common.device_tx_status = spinal_lib_dmasg_tx_status;
|
||||
priv->common.device_issue_pending = spinal_lib_dmasg_issue_pending;
|
||||
priv->common.device_prep_dma_cyclic = spinal_lib_dmasg_prep_dma_cyclic;
|
||||
priv->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
|
||||
|
||||
platform_set_drvdata(pdev, priv);
|
||||
|
||||
/* Initialize the channels */
|
||||
i = 0;
|
||||
for_each_child_of_node(node, child) {
|
||||
err = spinal_lib_dmasg_chan_probe(priv, child, i);
|
||||
if (err < 0)
|
||||
goto error;
|
||||
i++;
|
||||
}
|
||||
|
||||
/* Register the DMA engine with the core */
|
||||
dma_async_device_register(&priv->common);
|
||||
|
||||
err = of_dma_controller_register(node, of_dma_spinal_lib_xlate, priv);
|
||||
if (err < 0) {
|
||||
dev_err(&pdev->dev, "Unable to register DMA to DT\n");
|
||||
dma_async_device_unregister(&priv->common);
|
||||
goto error;
|
||||
}
|
||||
|
||||
|
||||
dev_info(&pdev->dev, "Probe success\n");
|
||||
|
||||
return 0;
|
||||
|
||||
error:
|
||||
dev_info(&pdev->dev, "Probe failure :(\n");
|
||||
for (i = 0; i < priv->chan_count; i++)
|
||||
spinal_lib_dmasg_chan_remove(&priv->chan[i]);
|
||||
|
||||
return err;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int spinal_lib_dmasg_remove(struct platform_device *pdev)
|
||||
{
|
||||
//printk("spinal_lib_dmasg_remove\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static const struct of_device_id spinal_lib_dmasg_of_ids[] = {
|
||||
{ .compatible = "spinal,lib-dmasg"},
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, spinal_lib_dmasg_of_ids);
|
||||
|
||||
static struct platform_driver spinal_lib_vdma_driver = {
|
||||
.driver = {
|
||||
.name = "spinal,lib-dmasg",
|
||||
.of_match_table = spinal_lib_dmasg_of_ids,
|
||||
},
|
||||
.probe = spinal_lib_dmasg_probe,
|
||||
.remove = spinal_lib_dmasg_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(spinal_lib_vdma_driver);
|
||||
|
||||
MODULE_AUTHOR("Spinal");
|
||||
MODULE_DESCRIPTION("SpinalHDL DMASG driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Reference in New Issue
Block a user