Initial commit

.gitignore

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+mount/br2-efinix/
+mount/build_ti375c529

Dockerfile

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+FROM debian:bullseye
+
+RUN groupadd -g 1000 builduser && useradd -m -r -u 1000 -g builduser builduser
+
+RUN apt update -y
+RUN apt upgrade -y
+RUN apt install -y git jq python3 python3-pip file wget cpio unzip rsync bc dosfstools zip mtools libssl-dev gnutls-dev
+RUN pip3 install jinja2
+
+USER 1000:1000

mount/build.sh

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+#!/bin/bash
+
+git config --global user.email "you@example.com"
+git config --global user.name "Your Name"
+
+ls -la ~
+ls -la /home
+
+git clone https://github.com/Efinix-Inc/br2-efinix.git
+cd br2-efinix
+git checkout 58839740f9bc62841e4b3b7c6e478fb06bf7e408
+source init.sh ti375c529 ../soc.h -p -e
+make -j16
+
+bash

mount/soc.h

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+#ifndef SOC_H
+#define SOC_H
+#define SYSTEM_RISCV_ISA_RV32I 1
+#define SYSTEM_RISCV_ISA_EXT_M 1
+#define SYSTEM_RISCV_ISA_EXT_A 1
+#define SYSTEM_RISCV_ISA_EXT_C 1
+#define SYSTEM_RISCV_ISA_EXT_F 1
+#define SYSTEM_RISCV_ISA_EXT_D 1
+#define SYSTEM_RISCV_ISA_EXT_ZICSR 1
+#define SYSTEM_RISCV_ISA_EXT_ZIFENCE 1
+#define SYSTEM_PLIC_SYSTEM_CORES_0_EXTERNAL_INTERRUPT 0
+#define SYSTEM_PLIC_SYSTEM_CORES_0_EXTERNAL_SUPERVISOR_INTERRUPT 1
+#define SYSTEM_PLIC_SYSTEM_CORES_1_EXTERNAL_INTERRUPT 2
+#define SYSTEM_PLIC_SYSTEM_CORES_1_EXTERNAL_SUPERVISOR_INTERRUPT 3
+#define SYSTEM_PLIC_SYSTEM_CORES_2_EXTERNAL_INTERRUPT 4
+#define SYSTEM_PLIC_SYSTEM_CORES_2_EXTERNAL_SUPERVISOR_INTERRUPT 5
+#define SYSTEM_PLIC_SYSTEM_CORES_3_EXTERNAL_INTERRUPT 6
+#define SYSTEM_PLIC_SYSTEM_CORES_3_EXTERNAL_SUPERVISOR_INTERRUPT 7
+#define SYSTEM_PLIC_USER_INTERRUPT_A_INTERRUPT 1
+#define SYSTEM_PLIC_USER_INTERRUPT_B_INTERRUPT 2
+#define SYSTEM_PLIC_USER_INTERRUPT_C_INTERRUPT 3
+#define SYSTEM_PLIC_USER_INTERRUPT_D_INTERRUPT 4
+#define SYSTEM_PLIC_USER_INTERRUPT_E_INTERRUPT 5
+#define SYSTEM_PLIC_USER_INTERRUPT_F_INTERRUPT 6
+#define SYSTEM_PLIC_USER_INTERRUPT_G_INTERRUPT 7
+#define SYSTEM_PLIC_USER_INTERRUPT_H_INTERRUPT 8
+#define SYSTEM_PLIC_USER_INTERRUPT_I_INTERRUPT 9
+#define SYSTEM_PLIC_USER_INTERRUPT_J_INTERRUPT 10
+#define SYSTEM_PLIC_USER_INTERRUPT_K_INTERRUPT 11
+#define SYSTEM_PLIC_USER_INTERRUPT_L_INTERRUPT 12
+#define SYSTEM_PLIC_USER_INTERRUPT_M_INTERRUPT 13
+#define SYSTEM_PLIC_USER_INTERRUPT_N_INTERRUPT 14
+#define SYSTEM_PLIC_USER_INTERRUPT_O_INTERRUPT 15
+#define SYSTEM_PLIC_USER_INTERRUPT_P_INTERRUPT 16
+#define SYSTEM_PLIC_USER_INTERRUPT_Q_INTERRUPT 17
+#define SYSTEM_PLIC_USER_INTERRUPT_R_INTERRUPT 18
+#define SYSTEM_PLIC_USER_INTERRUPT_S_INTERRUPT 19
+#define SYSTEM_PLIC_USER_INTERRUPT_T_INTERRUPT 20
+#define SYSTEM_PLIC_USER_INTERRUPT_U_INTERRUPT 21
+#define SYSTEM_PLIC_USER_INTERRUPT_V_INTERRUPT 22
+#define SYSTEM_PLIC_USER_INTERRUPT_W_INTERRUPT 23
+#define SYSTEM_PLIC_USER_INTERRUPT_X_INTERRUPT 24
+#define SYSTEM_PLIC_SYSTEM_AXI_A_INTERRUPT 30
+#define SYSTEM_PLIC_SYSTEM_USER_TIMER_1_INTERRUPTS_0 49
+#define SYSTEM_PLIC_SYSTEM_USER_TIMER_0_INTERRUPTS_0 50
+#define SYSTEM_RAM_A_SIZE 16384
+#define SYSTEM_CORES_0_CFU 1
+#define SYSTEM_CORES_0_FPU 1
+#define SYSTEM_CORES_0_MMU 1
+#define SYSTEM_CORES_0_ICACHE_WAYS 4
+#define SYSTEM_CORES_0_ICACHE_SIZE 16384
+#define SYSTEM_CORES_0_BYTES_PER_LINE 64
+#define SYSTEM_CORES_0_DCACHE_WAYS 4
+#define SYSTEM_CORES_0_DCACHE_SIZE 16384
+#define SYSTEM_CORES_0_BYTES_PER_LINE 64
+#define SYSTEM_CORES_0_SUPERVISOR 1
+#define SYSTEM_CORES_1_CFU 1
+#define SYSTEM_CORES_1_FPU 1
+#define SYSTEM_CORES_1_MMU 1
+#define SYSTEM_CORES_1_ICACHE_WAYS 4
+#define SYSTEM_CORES_1_ICACHE_SIZE 16384
+#define SYSTEM_CORES_1_BYTES_PER_LINE 64
+#define SYSTEM_CORES_1_DCACHE_WAYS 4
+#define SYSTEM_CORES_1_DCACHE_SIZE 16384
+#define SYSTEM_CORES_1_BYTES_PER_LINE 64
+#define SYSTEM_CORES_1_SUPERVISOR 1
+#define SYSTEM_CORES_2_CFU 1
+#define SYSTEM_CORES_2_FPU 1
+#define SYSTEM_CORES_2_MMU 1
+#define SYSTEM_CORES_2_ICACHE_WAYS 4
+#define SYSTEM_CORES_2_ICACHE_SIZE 16384
+#define SYSTEM_CORES_2_BYTES_PER_LINE 64
+#define SYSTEM_CORES_2_DCACHE_WAYS 4
+#define SYSTEM_CORES_2_DCACHE_SIZE 16384
+#define SYSTEM_CORES_2_BYTES_PER_LINE 64
+#define SYSTEM_CORES_2_SUPERVISOR 1
+#define SYSTEM_CORES_3_CFU 1
+#define SYSTEM_CORES_3_FPU 1
+#define SYSTEM_CORES_3_MMU 1
+#define SYSTEM_CORES_3_ICACHE_WAYS 4
+#define SYSTEM_CORES_3_ICACHE_SIZE 16384
+#define SYSTEM_CORES_3_BYTES_PER_LINE 64
+#define SYSTEM_CORES_3_DCACHE_WAYS 4
+#define SYSTEM_CORES_3_DCACHE_SIZE 16384
+#define SYSTEM_CORES_3_BYTES_PER_LINE 64
+#define SYSTEM_CORES_3_SUPERVISOR 1
+#define SYSTEM_BRIDGE_BMB 0x0
+#define SYSTEM_RAM_A_CTRL 0xf9000000
+#define SYSTEM_RAM_A_CTRL_SIZE 0x4000
+#define SYSTEM_BMB_PERIPHERAL_BMB 0xf8000000
+#define SYSTEM_BMB_PERIPHERAL_BMB_SIZE 0x1000000
+#define SYSTEM_PLIC_CTRL 0xf8c00000
+#define SYSTEM_PLIC_CTRL_SIZE 0x400000
+#define SYSTEM_CLINT_CTRL 0xf8b00000
+#define SYSTEM_CLINT_CTRL_SIZE 0x10000
+#define SYSTEM_USER_TIMER_1_CTRL 0xf8016000
+#define SYSTEM_USER_TIMER_1_CTRL_SIZE 0x1000
+#define SYSTEM_USER_TIMER_0_CTRL 0xf8015000
+#define SYSTEM_USER_TIMER_0_CTRL_SIZE 0x1000
+#define SYSTEM_DDR_BMB 0x1000
+#define SYSTEM_DDR_BMB_SIZE 0xe7fff000
+#define SYSTEM_AXI_A_BMB 0xe8000000
+#define SYSTEM_AXI_A_BMB_SIZE 0x10000000
+#define SYSTEM_GPIO_0_IO_CTRL_SIZE 0x100
+#define SYSTEM_GPIO_0_IO_CTRL 0xe8040000
+#define SYSTEM_SPI_0_IO_CTRL_SIZE 0x1000
+#define SYSTEM_SPI_0_IO_CTRL 0xe8030000
+#define SYSTEM_SPI_0_IO_PARAMETER_CMD_FIFO_DEPTH 256
+#define SYSTEM_SPI_0_IO_PARAMETER_RSP_FIFO_DEPTH 256
+#define SYSTEM_UART_0_IO_CTRL_SIZE 0x40
+#define SYSTEM_UART_0_IO_CTRL 0xe8010000
+#define SYSTEM_UART_0_IO_PARAMETER_UART_CTRL_CONFIG_DATA_WIDTH_MAX 8
+#define SYSTEM_UART_0_IO_PARAMETER_UART_CTRL_CONFIG_CLOCK_DIVIDER_WIDTH 20
+#define SYSTEM_UART_0_IO_PARAMETER_UART_CTRL_CONFIG_PRE_SAMPLING_SIZE 1
+#define SYSTEM_UART_0_IO_PARAMETER_UART_CTRL_CONFIG_SAMPLING_SIZE 5
+#define SYSTEM_UART_0_IO_PARAMETER_UART_CTRL_CONFIG_POST_SAMPLING_SIZE 2
+#define SYSTEM_UART_0_IO_PARAMETER_UART_CTRL_CONFIG_CTS_GEN 0
+#define SYSTEM_UART_0_IO_PARAMETER_UART_CTRL_CONFIG_RTS_GEN 0
+#define SYSTEM_UART_0_IO_PARAMETER_UART_CTRL_CONFIG_RX_SAMPLE_PER_BIT 8
+#define SYSTEM_UART_0_IO_PARAMETER_INIT_CONFIG_BAUDRATE 115200
+#define SYSTEM_UART_0_IO_PARAMETER_INIT_CONFIG_DATA_LENGTH 7
+#define SYSTEM_UART_0_IO_PARAMETER_INIT_CONFIG_PARITY NONE
+#define SYSTEM_UART_0_IO_PARAMETER_INIT_CONFIG_STOP ONE
+#define SYSTEM_UART_0_IO_PARAMETER_BUS_CAN_WRITE_CLOCK_DIVIDER_CONFIG 1
+#define SYSTEM_UART_0_IO_PARAMETER_BUS_CAN_WRITE_FRAME_CONFIG 1
+#define SYSTEM_UART_0_IO_PARAMETER_TX_FIFO_DEPTH 128
+#define SYSTEM_UART_0_IO_PARAMETER_RX_FIFO_DEPTH 128
+#define SYSTEM_I2C_0_IO_CTRL_SIZE 0x100
+#define SYSTEM_I2C_0_IO_CTRL 0xe8020000
+#define SYSTEM_CLINT_HZ 200000000
+#define IO_APB_SLAVE_0_INPUT_SIZE 65536
+#define IO_APB_SLAVE_0_INPUT 0xe8100000
+#define SYSTEM_PLIC_SYSTEM_UART_0_IO_INTERRUPT SYSTEM_PLIC_USER_INTERRUPT_A_INTERRUPT
+#define SYSTEM_PLIC_SYSTEM_SPI_0_IO_INTERRUPT SYSTEM_PLIC_USER_INTERRUPT_B_INTERRUPT
+#define SYSTEM_PLIC_SYSTEM_I2C_0_IO_INTERRUPT SYSTEM_PLIC_USER_INTERRUPT_C_INTERRUPT
+#define SYSTEM_PLIC_SYSTEM_GPIO_0_IO_INTERRUPTS_0 SYSTEM_PLIC_USER_INTERRUPT_D_INTERRUPT
+#define SYSTEM_PLIC_SYSTEM_GPIO_0_IO_INTERRUPTS_1 SYSTEM_PLIC_USER_INTERRUPT_E_INTERRUPT
+#define SYSTEM_HARD_RISCV_QC32 1
+#define FAMILY_TYPE TITANIUM
+
+#endif

run.sh

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+#!/bin/bash
+
+docker build -t br2-efinix .
+docker run --mount type=bind,source=./mount,target=/mount -w /mount br2-efinix ./build.sh