Byron Lathi 470bbc39ec Grand refactor

2026-04-18 19:19:55 -07:00

fpga

Grand refactor

2026-04-18 19:19:55 -07:00

src

Grand refactor

2026-04-18 19:19:55 -07:00

sub

Grand refactor

2026-04-18 19:19:55 -07:00

.gitignore

initial commit

2026-04-14 21:34:37 -07:00

.gitmodules

Factor out verilog6502 into its own submodule

2026-04-18 18:55:40 -07:00

init_env.sh

initial commit

2026-04-14 21:34:37 -07:00

requirements.txt

initial commit

2026-04-14 21:34:37 -07:00

Description

No description provided

2.4 MiB

Languages

Verilog 79.7%

Tcl 14.5%

SystemVerilog 5.7%