139 lines
4.9 KiB
JSON
139 lines
4.9 KiB
JSON
{
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"args": [
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"-o",
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"EfxSapphireHpSoc_slb",
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"--base_path",
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"/projects/SSE/llching/repo/efx_IP_master/efx_IP/efx_hard_soc/fpga/Ti375C529_devkit/ip",
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"--vlnv",
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{
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"vendor": "efinixinc.com",
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"library": "soc",
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"name": "efx_hard_soc",
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"version": "1.22.0"
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}
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],
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"conf": {
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"PLL_SOC_SYS_CLK_NAME": "\"soc_pll_sys_clk\"",
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"PLL_SOC_SYS_CLK_REF_FREQ_HIDDEN": "\"100\"",
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"PLL_SOC_SYS_CLK_REF_FREQ": "\"100\"",
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"PLL_SOC_SYS_CLKOUT1_PHASE": "\"0\"",
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"PLL_SOC_SYS_CLKOUT2_PHASE": "\"0\"",
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"PLL_SOC_MEM_CLK_NAME": "\"soc_pll_peri_clk\"",
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"PLL_SOC_MEM_CLK_REF_FREQ": "\"25\"",
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"PLL_SOC_MEM_CLKOUT1_FREQ": "\"250\"",
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"PLL_SOC_MEM_CLKOUT1_PHASE": "\"0\"",
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"PLL_SOC_MEM_CLKOUT2_FREQ": "\"250\"",
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"PLL_SOC_MEM_CLKOUT2_PHASE": "\"0\"",
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"PLL_LPDDR4_NAME": "\"soc_ddr_pll\"",
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"PLL_LPDDR4_REF_FREQ": "\"25\"",
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"PLL_LPDDR4_CLKOUT0_FREQ": "\"100\"",
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"PLL_LPDDR4_CLKOUT0_PHASE": "\"0\"",
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"PLL_LPDDR4_CLKOUT3_FREQ": "\"533\"",
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"PLL_LPDDR4_CLKOUT3_PHASE": "\"0\"",
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"DDR_DATA_WIDTH": "32",
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"DDR_MEMORY_DENSITY": "\"8G\"",
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"DDR_MEMORY_TYPE": "\"LPDDR4x\"",
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"DDR_PHYSICAL_RANK": "1",
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"DDR_PIN_NAME": "\"soc_ddr_inst1\"",
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"INTF_AXIM": "1'b0",
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"INTF_CI_0": "1'b0",
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"INTF_CI_1": "1'b0",
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"INTF_CI_2": "1'b0",
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"INTF_CI_3": "1'b0",
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"CO_DEBUG": "1'b0",
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"INTF_JTAG_TYPE": "0",
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"INTF_UINTR": "9",
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"PERI_SPI_0": "1'b1",
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"PERI_SPI_1": "1'b0",
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"PERI_SPI_2": "1'b0",
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"PERI_I2C_0": "1'b1",
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"PERI_I2C_1": "1'b0",
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"PERI_I2C_2": "1'b0",
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"PERI_GPIO_0": "1'b1",
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"PERI_GPIO_1": "1'b0",
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"PERI_WDT_0": "1'b1",
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"PERI_APB_0": "1'b1",
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"PERI_APB_1": "1'b0",
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"PERI_APB_2": "1'b0",
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"PERI_APB_3": "1'b0",
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"PERI_APB_4": "1'b0",
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"PERI_GEN": "1'b1",
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"PERI_UART_0": "1'b1",
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"PERI_UART_1": "1'b0",
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"PERI_UART_2": "1'b0",
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"PERI_GPIO_0_WIDTH": "4",
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"PERI_GPIO_1_WIDTH": "4",
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"PERI_APB_0_SIZE": "65536",
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"PERI_APB_1_SIZE": "4096",
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"PERI_APB_2_SIZE": "4096",
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"PERI_APB_3_SIZE": "4096",
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"PERI_APB_4_SIZE": "4096",
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"PERI_FREQ": "200",
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"APP_OVERWRITE": "1'b0",
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"APP_OVERWRITE_PATH": "\"''\"",
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"INTF_JTAG_TAP_SEL": "8",
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"INTF_AXIS": "1'b1",
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"PERI_PIN_ASSIGN": "1'b1",
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"PLL_SOC_MEM_RESOURCE": "\"PLL_TR0\"",
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"SYS_FREQ": "1000",
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"SYS_FREQ_HIDDEN": "1000",
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"PLL_SOC_SYS_CLKOUT3_FREQ": "\"250\"",
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"PLL_SOC_SYS_CLKOUT3_PHASE": "\"0\"",
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"PLL_SOC_MEM_CLKOUT3_FREQ": "\"250\"",
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"PLL_SOC_MEM_CLKOUT3_PHASE": "\"0\"",
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"PLL_SOC_MEM_CLKOUT4_PHASE": "\"0\"",
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"PLL_SOC_SYS_RESOURCE": "\"PLL_BL0\"",
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"PLL_LPDDR4_RESOURCE": "\"PLL_BL2\"",
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"PLL_RES_ASSIGN": "1'b0",
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"PLL_SOC_SYS_CLKOUT0_FREQ": "\"100\"",
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"PLL_SOC_SYS_CLKOUT0_PHASE": "\"0\"",
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"PLL_SOC_MEM_CLKOUT0_FREQ": "\"100\"",
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"PLL_SOC_MEM_CLKOUT0_PHASE": "\"0\"",
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"PLL_LPDDR4_CLKOUT1_FREQ": "\"33\"",
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"PLL_LPDDR4_CLKOUT1_PHASE": "\"0\"",
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"MEM_FREQ": "250",
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"AXIM_FREQ": "250",
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"CFU_FREQ": "125",
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"DDR_FREQ": "800",
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"PLL_RES_ASSIGN_2": "1'b0",
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"DDR_RES_ASSIGN": "1'b0",
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"PERI_RES_ASSIGN": "1'b0",
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"PLL_SOC_SYS_EXT_CLK_SRC": "1",
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"PLL_SOC_MEM_EXT_CLK_SRC": "0",
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"PERI_SDHC": "1'b0",
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"PERI_TSEMAC": "1'b0",
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"SW_FTDI_CH_NUM": "6011",
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"SW_APP_SIZE": "2044",
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"SW_APP_SIZE_CUSTOM": "0",
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"SW_STACK_SIZE": "8",
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"SW_STACK_SIZE_CUSTOM": "0",
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"SW_BOARD": "\"Ti375C529 Development Kit\"",
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"SW_BOARD_CUSTOM": "\"\"",
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"SW_FTDI_TARGET_CH": "1",
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"SW_FTDI_CH_NUM_SOFT": "6011",
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"SW_FTDI_TARGET_CH_SOFT": "0",
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"SW_FRTOS_APP_SIZE": "16380",
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"SW_FRTOS_APP_SIZE_CUSTOM": "0",
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"SW_FRTOS_STACK_SIZE": "4",
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"SW_FRTOS_STACK_SIZE_CUSTOM": "0",
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"PACKAGE_TYPE": "\"529\"",
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"FAMILY_TYPE": "\"TITANIUM\"",
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"AXI_PIPELINE": "1'b0",
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"AXI_WRITE_BUFFER": "1'b0"
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},
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"output": {
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"external_script_Peripheral_Generator": [],
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"external_source_source": [
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"EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.vhd",
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"EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.v",
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"EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb.v",
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"EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_define.vh"
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],
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"external_script_PT_Configuration": [],
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"external_script_Peripheral_Post_Script": [],
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"external_script_Embedded_SW": []
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},
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"ooc_synthesis": {},
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"sw_version": "2025.2.272",
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"generated_date": "2025-10-16T10:03:46.765007+00:00"
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} |