Skip to content
Snippets Groups Projects

Repository graph

You can move around the graph by using the arrow keys.
Select Git revision
  • 12-primitive-processor
  • 13-unified-pipeline
  • master default protected
3 results
Created with Raphaël 2.2.08Apr731231Mar302927262524232221201817161514131211planning with stub modules13-unified-pipe…13-unified-pipelineRework with new resets and valids, wipAdd resets and ready input to mathNew vertex generatorChange vertex generator control to only read the source, not length or destinationAdd 9-BoundingBoxAdd unified pipeline experimentMake fpga build manual12-primitive-pr…12-primitive-processorAdd fp32 edge functionUpdate docsMerge branch 'axi_debugging' into 'master'mastermasterAxi debuggingChanges to get it to work on the FPGA. Change BAR to 256MB and 1MB. Add ILA for datapathAdd verilog-axis to vertex_generator sim sourcesAdd fifo between datapath and write fsm, get top level sim workingcompile cleanAdd fpga stubs, change interconnect, start integrationCreate interconnect, add vertex gen to topGet ram workingGo back to axi pcieAdd fpga build to ciChange pcie aximm to xdmaGet fpga to compileFix gitignores, add mig prj filesStart working on initial FPGA infrastructureAdd ip and initial pin placementPrint a plot of the transformed points like the software model doesChange write fsm to write 4 dwords instead of 3, for visibility/flags. end to end checkAdd write fsm and harnessAdd ready inputAdd read fsm testingRename output folder of datapath synthesisAdd vertex_generator top harnesschange test namesAdd wait state for outputs to be written before asserting startfinish pointer chasing state machineMake fp32_t a packed structAdd back hierarchical for pre optimization synthesisChoose correct part for synthesys resultsstart reading the descriptor