fix axi_intf, add to sources

axi_intf.sv

 interface axi_intf #(
     parameter AXI_DATA_WIDTH=32,
     parameter AXI_ADDR_WIDTH=32,
-    localparam AXI_STRB_WIDTH=(AXIL_DATA_WIDTH+7)/8,
+    localparam AXI_STRB_WIDTH=(AXI_DATA_WIDTH+7)/8,
     parameter AXI_AWUSER_WIDTH=1,
     parameter AXI_WUSER_WIDTH=1,
     parameter AXI_BUSER_WIDTH=1,
     parameter AXI_ARUSER_WIDTH=1,
     parameter AXI_RUSER_WIDTH=1,
-    parameter AXI_ID_WIDTH=1,
+    parameter AXI_ID_WIDTH=1
 );    
     
-    logic [AXI_ID_WIDTH-1:0]      s_axi_awid;
-    logic [AXI_ADDR_WIDTH-1:0]    s_axi_awaddr;
-    logic [7:0]                   s_axi_awlen;
-    logic [2:0]                   s_axi_awsize;
-    logic [1:0]                   s_axi_awburst;
-    logic                         s_axi_awlock;
-    logic [3:0]                   s_axi_awcache;
-    logic [2:0]                   s_axi_awprot;
-    logic [3:0]                   s_axi_awqos;
-    logic [3:0]                   s_axi_awregion;
-    logic [AWUSER_WIDTH-1:0]      s_axi_awuser;
-    logic                         s_axi_awvalid;
-    logic                         s_axi_awready;
-    logic [AXI_DATA_WIDTH-1:0]    s_axi_wdata;
-    logic [AXI_STRB_WIDTH-1:0]    s_axi_wstrb;
-    logic                         s_axi_wlast;
-    logic [AXI_WUSER_WIDTH-1:0]   s_axi_wuser;
-    logic                         s_axi_wvalid;
-    logic                         s_axi_wready;
-    logic [AXI_ID_WIDTH-1:0]      s_axi_bid;
-    logic [1:0]                   s_axi_bresp;
-    logic [AXI_BUSER_WIDTH-1:0]   s_axi_buser;
-    logic                         s_axi_bvalid;
-    logic                         s_axi_bready;
-    logic [AXI_ID_WIDTH-1:0]      s_axi_arid;
-    logic [AXI_ADDR_WIDTH-1:0]    s_axi_araddr;
-    logic [7:0]                   s_axi_arlen;
-    logic [2:0]                   s_axi_arsize;
-    logic [1:0]                   s_axi_arburst;
-    logic                         s_axi_arlock;
-    logic [3:0]                   s_axi_arcache;
-    logic [2:0]                   s_axi_arprot;
-    logic [3:0]                   s_axi_arqos;
-    logic [3:0]                   s_axi_arregion;
-    logic [AXI_ARUSER_WIDTH-1:0]  s_axi_aruser;
-    logic                         s_axi_arvalid;
-    logic                         s_axi_arready;
-    logic [AXI_ID_WIDTH-1:0]      s_axi_rid;
-    logic [AXI_DATA_WIDTH-1:0]    s_axi_rdata;
-    logic [1:0]                   s_axi_rresp;
-    logic                         s_axi_rlast;
-    logic [AXI_RUSER_WIDTH-1:0]   s_axi_ruser;
-    logic                         s_axi_rvalid;
-    logic                         s_axi_rready;
+    logic [AXI_ID_WIDTH-1:0]      awid;
+    logic [AXI_ADDR_WIDTH-1:0]    awaddr;
+    logic [7:0]                   awlen;
+    logic [2:0]                   awsize;
+    logic [1:0]                   awburst;
+    logic                         awlock;
+    logic [3:0]                   awcache;
+    logic [2:0]                   awprot;
+    logic [3:0]                   awqos;
+    logic [3:0]                   awregion;
+    logic [AXI_AWUSER_WIDTH-1:0]      awuser;
+    logic                         awvalid;
+    logic                         awready;
+    logic [AXI_DATA_WIDTH-1:0]    wdata;
+    logic [AXI_STRB_WIDTH-1:0]    wstrb;
+    logic                         wlast;
+    logic [AXI_WUSER_WIDTH-1:0]   wuser;
+    logic                         wvalid;
+    logic                         wready;
+    logic [AXI_ID_WIDTH-1:0]      bid;
+    logic [1:0]                   bresp;
+    logic [AXI_BUSER_WIDTH-1:0]   buser;
+    logic                         bvalid;
+    logic                         bready;
+    logic [AXI_ID_WIDTH-1:0]      arid;
+    logic [AXI_ADDR_WIDTH-1:0]    araddr;
+    logic [7:0]                   arlen;
+    logic [2:0]                   arsize;
+    logic [1:0]                   arburst;
+    logic                         arlock;
+    logic [3:0]                   arcache;
+    logic [2:0]                   arprot;
+    logic [3:0]                   arqos;
+    logic [3:0]                   arregion;
+    logic [AXI_ARUSER_WIDTH-1:0]  aruser;
+    logic                         arvalid;
+    logic                         arready;
+    logic [AXI_ID_WIDTH-1:0]      rid;
+    logic [AXI_DATA_WIDTH-1:0]    rdata;
+    logic [1:0]                   rresp;
+    logic                         rlast;
+    logic [AXI_RUSER_WIDTH-1:0]   ruser;
+    logic                         rvalid;
+    logic                         rready;
 
     modport MASTER (
         output awid,

sources.list

 ip_intf.sv
 eth_intf.sv
 axil_intf.sv
+axi_intf.sv
 axis_intf.sv
 cpuif_intf.sv
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