Make synthesis optional

.gitlab-ci.yml

@@ -7,6 +7,7 @@ stages:
 
 build:
   stage: build
+  when: manual
   tags:
     - efinity
     - linux
@@ -18,6 +19,7 @@ build:
 
 sim:
   stage: sim
+  needs: []
   tags:
     - linux
     - efinity

hw/super6502_fpga/super6502_fpga.xml

@@ -204,6 +204,11 @@
         <efx:design_file name="src/sub/interfaces/axis_intf.sv" version="default" library="default" />
         <efx:design_file name="src/sub/interfaces/ip_intf.sv" version="default" library="default" />
         <efx:design_file name="src/sub/interfaces/eth_intf.sv" version="default" library="default" />
+        <efx:design_file name="src/sub/my-fifos/src/axis_saf.sv" version="default" library="default"/>
+        <efx:design_file name="src/sub/my-fifos/src/dpram.sv" version="default" library="default"/>
+        <efx:design_file name="src/sub/my-fifos/src/fifo_fwft.sv" version="default" library="default"/>
+        <efx:design_file name="src/sub/my-fifos/src/fifo.sv" version="default" library="default"/>
+        <efx:design_file name="src/sub/my-fifos/src/fwft_adapter.sv" version="default" library="default"/>
         <efx:top_vhdl_arch name="" />
     </efx:design_info>
     <efx:constraint_info>