Increase seq when sending fins

hw/super6502_fpga/src/sub/network_processor/sim/cocotb/tests/scapy_irl_test.py

@@ -94,7 +94,7 @@ def ip_to_hex(ip: str) -> int:
 
     return result
 
-# @cocotb.test()
+@cocotb.test()
 async def test_irl(dut):
     tb = TB(dut)
 
@@ -270,11 +270,19 @@ async def test_irl(dut):
 
     await tb.mii_phy.rx.send(GmiiFrame.from_payload(tcp_fin.build()))
 
+    tb.log.info("Expecting to get ACK from DUT")
+
+    ip_packet = await read_tcp_from_dut()
+
+    t.send(ip_packet)
+
+    tb.log.info("Expecting to get FINACK from DUT")
+
     ip_packet = await read_tcp_from_dut()
 
     t.send(ip_packet)
 
-    tb.log.info("Expecting to send last ACK here")
+    tb.log.info("Expecting to get ACK from host")
 
     while True:
         pkt = t.recv()
@@ -455,4 +463,4 @@ async def test_close(dut):
     tb.log.info("Sending packet to host")
     t.send(ip_packet)
 
-    await Timer(Decimal(CLK_PERIOD_NS * 10000), units='ns')
\ No newline at end of file
+    await Timer(Decimal(CLK_PERIOD_NS * 20000), units='ns')
\ No newline at end of file

hw/super6502_fpga/src/sub/network_processor/src/tcp_rx_ctrl.sv

@@ -54,6 +54,7 @@ always_comb begin
         if (i_flags == 8'h11) begin
             rx_msg_next = RX_MSG_RECV_FIN;
             rx_msg_valid_next = '1;
+            ack_num_next = i_seq_number + 1;
         end
 
         if (i_flags == 8'h10) begin

hw/super6502_fpga/src/sub/network_processor/src/tcp_state_manager.sv

@@ -126,7 +126,9 @@ always_comb begin
         WAIT_CLOSE: begin
             o_tx_ctrl = TX_CTRL_SEND_FIN;
             o_tx_ctrl_valid = '1;
-            tcp_state_next = LAST_ACK;
+            if (i_tx_ctrl_ack) begin        // we should be doing this other places too...
+                tcp_state_next = LAST_ACK;
+            end
         end
 
         LAST_ACK: begin

hw/super6502_fpga/src/sub/network_processor/src/tcp_tx_ctrl.sv

@@ -130,7 +130,7 @@ always_comb begin
 
             if (i_packet_done) begin
                 state_next = IDLE;
-                seq_num_next = seq_num + s_axis_len;
+                seq_num_next = seq_num + 1;
             end
         end
     endcase

verilog-ethernet @ e00d2466

-Subproject commit 13f6d6137d7c29f0482d5a692c5dcbb48cbec46d
+Subproject commit e00d2466b0f2ce4e10653e7a40fdc814bf422d21