Big update to try and pass timing. reduces tcp streams to 1

hw/super6502_fpga/src/rtl/super_6502_fpga.sv

hw/super6502_fpga/src/sub/interfaces

.../sub/network_processor/sim/cocotb/tests/scapy_irl_test.py

hw/super6502_fpga/src/sub/network_processor/sources.list

...6502_fpga/src/sub/network_processor/src/axil_reg_slice.sv

...r6502_fpga/src/sub/network_processor/src/checksum_calc.sv

...sub/network_processor/src/ip_pipeline_register_wrapper.sv

...2_fpga/src/sub/network_processor/src/network_processor.sv

...pga/src/sub/network_processor/src/tcp_packet_generator.sv

...per6502_fpga/src/sub/network_processor/src/tcp_rx_ctrl.sv

...2_fpga/src/sub/network_processor/src/tcp_state_manager.sv

...uper6502_fpga/src/sub/network_processor/src/tcp_stream.sv

...per6502_fpga/src/sub/network_processor/src/tcp_tx_ctrl.sv

hw/super6502_fpga/src/sub/verilog-ethernet

hw/super6502_fpga/super6502_fpga.xml