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Commit 766fe72d authored by Byron Lathi's avatar Byron Lathi
Browse files

add fin

parent 00d982a5
Branches 99-respond-to-fin-packet
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3 merge requests!79Draft: Resolve "Respond to FIN packet",!77Calculate checksum for tcp data also,!74Resolve "Network Processor"
Pipeline #764 failed
from http import server
from scapy.layers.inet import Ether, IP, TCP
from scapy.layers.l2 import ARP
from scapy.data import IP_PROTOS
from scapy import sendrecv
......@@ -205,6 +206,44 @@ async def test_irl(dut):
con, addr = serversocket.accept()
con.close()
serversocket.close()
while True:
pkt = t.recv()
if (pkt.proto == IP_PROTOS.tcp):
break
print(pkt)
tcp_fin = Ether(dst=dut_mac, src=tb_mac) / pkt
await tb.mii_phy.rx.send(GmiiFrame.from_payload(tcp_fin.build()))
resp = await tb.mii_phy.tx.recv() # type: GmiiFrame
packet = Ether(resp.get_payload())
tb.log.info(f"Packet Type: {packet.type:x}")
ip_packet = packet.payload
assert isinstance(ip_packet, IP)
tcp_packet = ip_packet.payload
assert isinstance(tcp_packet, TCP)
tb.log.info(f"Source Port: {tcp_packet.sport}")
tb.log.info(f"Dest Port: {tcp_packet.dport}")
tb.log.info(f"Seq: {tcp_packet.seq}")
tb.log.info(f"Ack: {tcp_packet.ack}")
tb.log.info(f"Data Offs: {tcp_packet.dataofs}")
tb.log.info(f"flags: {tcp_packet.flags}")
tb.log.info(f"window: {tcp_packet.window}")
tb.log.info(f"Checksum: {tcp_packet.chksum}")
t.send(ip_packet)
return
# Construct a descriptor in memry
tb.axil_ram.write_dword(0x00000000, 0x00001000)
tb.axil_ram.write_dword(0x00000004, 64)
......@@ -228,4 +267,4 @@ async def test_irl(dut):
# con.recv(64)
serversocket.close()
\ No newline at end of file
serversocket.close()
......@@ -128,6 +128,10 @@ always_comb begin
m_ip.ip_payload_axis_tdata = pipe[31:24];
valid = '1;
if (pipe_last[3] && pipe_valid[3]) begin
state_next = PORTS;
end
end
endcase
end
......
......@@ -32,12 +32,17 @@ end
always_comb begin
if (i_hdr_valid) begin
if (i_flags & 8'h12) begin
if (i_flags == 8'h12) begin
o_rx_msg = RX_MSG_RECV_SYNACK;
o_rx_msg_valid = '1;
ack_num_next = i_seq_number + 1;
end
if (i_flags == 8'h11) begin
o_rx_msg = RX_MSG_RECV_FIN;
o_rx_msg_valid = '1;
end
end
end
......
......@@ -84,6 +84,14 @@ always_comb begin
end
ESTABLISHED: begin
if (i_rx_msg_valid && i_rx_msg == RX_MSG_RECV_FIN) begin
o_tx_ctrl = TX_CTRL_SEND_FIN;
o_tx_ctrl_valid = '1;
tcp_state_next = LAST_ACK;
end
end
LAST_ACK: begin
end
endcase
......
......@@ -43,7 +43,7 @@ localparam FLAG_CWR = (1 << 7);
logic [31:0] seq_num, seq_num_next;
assign o_seq_number = seq_num;
enum logic [2:0] {IDLE, SEND_SYN, SEND_ACK, SEND_DATA} state, state_next;
enum logic [2:0] {IDLE, SEND_SYN, SEND_ACK, SEND_FIN, SEND_DATA} state, state_next;
always_ff @(posedge i_clk) begin
if (i_rst) begin
......@@ -75,6 +75,7 @@ always_comb begin
case (i_tx_ctrl)
TX_CTRL_SEND_SYN: state_next = SEND_SYN;
TX_CTRL_SEND_ACK: state_next = SEND_ACK;
TX_CTRL_SEND_FIN: state_next = SEND_FIN;
endcase
end
......@@ -113,6 +114,17 @@ always_comb begin
seq_num_next = seq_num + s_axis_len;
end
end
SEND_FIN: begin
o_flags = FLAG_ACK | FLAG_FIN;
o_ip_len = 16'd40 + s_axis_len; // default length of IP packet
o_hdr_valid = '1;
if (i_packet_done) begin
state_next = IDLE;
seq_num_next = seq_num + s_axis_len;
end
end
endcase
end
......
......@@ -8,12 +8,11 @@ export KICAD7_SYMBOL_DIR=$REPO_TOP/hw/kicad_library/symbols
export KICAD7_3DMODEL_DIR=$REPO_TOP/hw/kicad_library/3dmodels
export KICAD7_FOOTPRINT_DIR=$REPO_TOP/hw/kicad_library/footprints
#module load efinity/2023.1
module load verilator
module load gtkwave/3.3_gtk3
python3.11 -m venv .user_venv
python3.12 -m venv .user_venv
. .user_venv/bin/activate
pip install -r requirements.txt
module load efinity/2023.1
module load verilator
module load gtkwave/3.3_gtk3
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