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Unverified Commit 84a31d14 authored by Byron Lathi's avatar Byron Lathi
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Add sd card test program

parent 1cb54d6b
Branches efinix_sdcard
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"board": {
"active_layer": 0,
"active_layer_preset": "All Layers",
"auto_track_width": true,
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
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"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
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0
This diff is collapsed.
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Thu January 12 2023 21:31:38" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project name="super6502" description="" last_change_date="Fri January 13 2023 13:10:59" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2022.2.322" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T20F256"/>
......@@ -8,11 +8,6 @@
<efx:design_info def_veri_version="sv_09" def_vhdl_version="vhdl_2008">
<efx:top_module name="super6502"/>
<efx:design_file name="super6502.sv" version="default" library="default"/>
<efx:design_file name="ip/bram/bram_primitive.v" version="verilog_2k" library="default"/>
<efx:design_file name="ip/bram/bram_decompose.vh" version="verilog_2k" library="default"/>
<efx:design_file name="ip/bram/bram_ini.vh" version="verilog_2k" library="default"/>
<efx:design_file name="ip/bram/efx_single_port_ram.v" version="verilog_2k" library="default"/>
<efx:design_file name="ip/bram/bram_wrapper_mwm.v" version="verilog_2k" library="default"/>
<efx:design_file name="leds.sv" version="default" library="default"/>
<efx:design_file name="addr_decode.sv" version="default" library="default"/>
<efx:design_file name="sdram_adapter.sv" version="default" library="default"/>
......@@ -23,6 +18,7 @@
<efx:design_file name="uart_wrapper.sv" version="default" library="default"/>
<efx:design_file name="sd_controller.sv" version="default" library="default"/>
<efx:design_file name="crc7.sv" version="default" library="default"/>
<efx:design_file name="rom.sv" version="default" library="default"/>
<efx:top_vhdl_arch name=""/>
</efx:design_info>
<efx:constraint_info>
......
TARGETS=stacktest runram timer timer_irq multiplier divider uart uart2 sdcard
SRC=$(wildcard *.s)
DIR=../ip/bram
DIR=..
all: $(TARGETS)
......@@ -10,7 +10,7 @@ $(TARGETS): $(SRC)
install:
cp $(TARGET).hex $(DIR)/init_hex.mem
cd $(DIR);python3 efx_mem_init_script.py hex init_hex.mem
# cd $(DIR);python3 efx_mem_init_script.py hex init_hex.mem
clean:
......
.importzp sp, sreg, ptr1, tmp1, tmp2, tmp3, tmp4
.importzp sp, sreg, ptr1, ptr2, tmp1, tmp2, tmp3, tmp4
.export _sd_card_command
.export _sd_card_resp
.autoimport on
.zeropage
_resp: .res 4
.code
......@@ -12,62 +15,29 @@ SD_ARG = $efd8
SD_CMD = $efdc
SD_DATA = $efdd
_resp = $10
main:
@cmd0:
jsr stztmp ; arg = 0
lda #$00 ; cmd = 0
jsr _sd_card_command
nop ; no resp, so need to wait for cmd to finish
lda #$18
@delay: dec
bne @delay
jsr _sd_init
@end:
wai
bra @end
@cmd8:
lda #$aa
sta tmp1
inc tmp2 ; arg = 000001aa
lda #$08 ; cmd = 8
jsr _sd_card_command
lda #<_resp
ldx #>_resp
jsr _sd_card_resp_timeout
lda _resp
beq @cmd8
end:
wai
bra end
stztmp:
stz tmp1
stz tmp2
stz tmp3
stz tmp4
rts
; Send sd card command.
; command is in A register, the args are in tmp1-4 le
_sd_card_command:
pha ; store cmd
lda tmp1 ; write args
sta SD_ARG
lda tmp2
sta SD_ARG+1
lda tmp3
sta SD_ARG+2
lda tmp4
sta SD_ARG+3
pla ; write cmd
sta SD_CMD
rts
pha ; store cmd
lda tmp1 ; write args
sta SD_ARG
lda tmp2
sta SD_ARG+1
lda tmp3
sta SD_ARG+2
lda tmp4
sta SD_ARG+3
pla ; write cmd
sta SD_CMD
rts
; void sd_card_resp(uint32_t* resp);
_sd_card_resp:
......@@ -99,9 +69,7 @@ _sd_card_resp:
iny
sta (ptr1),y
ply
rts
rts
; int sd_card_resp_timeout(uint32_t* resp);
_sd_card_resp_timeout:
phy
......@@ -144,6 +112,180 @@ _sd_card_resp_timeout:
ldx #$ff
rts
_sd_card_wait_for_data:
pha
@1: lda SD_CMD ; wait for status flag
and #$02
beq @1
pla
rts
; void sd_init();
;
_sd_init:
@cmd0:
stz tmp1
stz tmp2
stz tmp3
stz tmp4 ; arg = 0
lda #$00 ; cmd = 0
jsr _sd_card_command
nop ; no resp, so need to wait for cmd to fin
lda #$12
@delay: dec
bne @delay
@cmd8:
lda #$aa
sta tmp1
inc tmp2 ; arg = 000001aa
lda #$08 ; cmd = 8
jsr _sd_card_command
lda #<_resp
ldx #>_resp
jsr _sd_card_resp_timeout
lda _resp
beq @cmd8
@acmd41:
stz tmp1
stz tmp2 ; arg = 00000000
stz tmp3
stz tmp4
lda #$37 ; cmd = 55
jsr _sd_card_command
lda #<_resp
ldx #>_resp
jsr _sd_card_resp ; resp
lda #$18
sta tmp3
lda #$40
sta tmp4 ; arg = 40180000
lda #$29 ; cmd = 41
jsr _sd_card_command
lda #<_resp
ldx #>_resp
jsr _sd_card_resp ; resp
lda _resp+3
beq @acmd41
stz tmp3
stz tmp4
lda #$02 ; arg = 0
jsr _sd_card_command ; cmd = 2
lda #$25 ; don't trust read flag, this is a long r
@1: dec
bne @1
lda #<_resp
ldx #>_resp
jsr _sd_card_resp ; resp
stz tmp1
stz tmp2
stz tmp3
stz tmp4 ; arg = 0
lda #$03 ; cmd = 3
jsr _sd_card_command
stz _resp
stz _resp+1
stz _resp+2
stz _resp+3 ; resp = 0
lda #<_resp
ldx #>_resp
jsr _sd_card_resp ; resp
lda _resp+2 ; return resp >> 16
ldx _resp+3
rts
; uint16_t sd_select_card(uint16_t rca)
;
_sd_select_card:
stz tmp1
stz tmp2
sta tmp3
stx tmp4 ; arg = rca << 16
lda #$07 ; cmd = 7
jsr _sd_card_command
lda #<_resp
ldx #>_resp
jsr _sd_card_resp ; resp
lda _resp ; return resp
ldx _resp+1
rts
; uint16_t sd_get_status(uint16_t rca)
; (this is basically the same as select card...)
_sd_get_status:
stz tmp1
stz tmp2
sta tmp3
stx tmp4 ; arg = rca << 16
lda #$0d ; cmd = 13
jsr _sd_card_command
lda #<_resp
ldx #>_resp
jsr _sd_card_resp ; resp
lda _resp ; return resp
ldx _resp+1
rts
; void sd_readblock(uint32_t addr, void* buf)
;
_sd_readblock:
sta ptr2 ; ptr2 = &buf
stx ptr2+1
ldy #$3
lda (sp),y
sta tmp4
dey
lda (sp),y
sta tmp3
dey
lda (sp),y
sta tmp2
lda (sp)
sta tmp1
lda #$11 ; cmd = 17
jsr _sd_card_command
lda #<_resp
ldx #>_resp
jsr _sd_card_resp ; resp
jsr _sd_card_wait_for_data
ldy #$00
sty tmp1
@loop: lda SD_DATA ; loop 256 times
sta (ptr2),y
iny
bne @loop
lda tmp1
bne @end ; stop after second loop
inc ptr2+1 ; inc high byte of ptr (+256)
inc tmp1
bra @loop ; y is already zer0
@end: jsr incsp4 ; addr was on stack
rts
.segment "VECTORS"
.addr main
......
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