Use verilator for simulation

Verilator is a lot faster and supports more features than iverilog.

added Simulation label

assigned to @bslathi19

created branch 92-use-verilator-for-simulation to address this issue

mentioned in merge request !73 (closed)

the sdram model is not behaving nicely with verilator. This is the line in question:

if (Data_out_enable == 1'b0) begin
    Dq_reg <= #tOH {DQ_BITS{1'bz}};
end

and this guy says that verilator does not support nonblocking tristate.

So what we need to do is set a value that is not tristate, and have the tristate stuff done combinationally outside of the clocked blocks.

Also, just changing this to a blocking assignment does not work.

Could we use Dan's sdram controller and sdram model?

https://github.com/ZipCPU/xulalx25soc/blob/master/bench/cpp/sdramsim.cpp

Actually the sdram controller is wishbone so I don't want to use it. However, I still want to build my own at some point.

That sim is for a c++ based testbench though, not a verilog one. Maybe there is a different one I can use? Does he have any other projects that use sdram?

So it looks like the problem is that we cannot read from sdram. Wonderful

We could just have the sdram model not be bidirectional, since the top level of our FPGA has to have them split anyway...

Yeah I think we should just leave well enough alone (even if it is not actually that well). It seems like the best way to do this is to have the model in C, and then call it there. However, I would rather be working on design than on simulation architecture.

closed

I know this is already closed, but if we can stub out the DDR and replace it with an axi4 sram of the same size, we should still be able to simulate faster with iverilog even if it will not be cycle accurate. It looks like iverilog is not a fan of unpacked structs which are generated by peak-rdl

mentioned in issue #93 (closed)