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Add basic sim

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This commit is contained in:
Byron Lathi
2024-03-03 17:06:10 -08:00
parent ab9da189d1
commit 01b1ecbcac
9 changed files with 152 additions and 1 deletions
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3
.gitmodules vendored
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@@ -7,3 +7,6 @@
[submodule "sw/toolchain/cc65"]
path = sw/toolchain/cc65
url = ../cc65.git
[submodule "hw/super6502_fpga/src/sim/sub/verilog-6502"]
path = hw/super6502_fpga/src/sim/sub/verilog-6502
url = ../verilog-6502.git