Build software correctly, ignore debugger files
This commit is contained in:
Byron Lathi
20
.gitignore
vendored
20
.gitignore
vendored
@@ -1,4 +1,22 @@
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.vscode
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.~lock*
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.user_venv/
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.user_venv/
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# Software build files
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*.map
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*.list
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*.bin
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*.o
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# Efinix Debugger
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*.log*
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*.vcd
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*.gtkw
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*debug_profile*
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*.mem
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5
Makefile
5
Makefile
@@ -21,12 +21,13 @@ $(INIT_HEX): toolchain script/generate_rom_image.py $(HEX)
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python script/generate_rom_image.py -i $(HEX) -o $@
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$(HEX):
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$(MAKE) -C sw/$(ROM) $(notdir $@)
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$(MAKE) -C sw/$(ROM_TARGET) $(notdir $@)
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.PHONY: clean
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clean:
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$(MAKE) -C hw/super6502_fpga $@
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$(MAKE) -C sw/$(ROM_TARGET) clean
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.PHONY: distclean
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distclean: clean
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$(MAKE) -C sw/toolchain/cc65 clean
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$(MAKE) -C sw/toolchain/cc65 clean
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@@ -1,65 +0,0 @@
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@00000000
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8d00a9
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200cd02
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801a03d0
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fe80f5
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ff000000
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ff00ff00
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@@ -1,4 +1,4 @@
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<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Sun Mar 03 2024 12:51:24 PM" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
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<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Sun Mar 03 2024 14:48:43" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
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<efx:device_info>
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<efx:family name="Trion" />
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<efx:device name="T20F256" />
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@@ -81,9 +81,4 @@
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<efx:param name="cold_boot" value="off" value_type="e_bool" />
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<efx:param name="cascade" value="off" value_type="e_option" />
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</efx:bitstream_generation>
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<efx:debugger>
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<efx:param name="work_dir" value="work_dbg" value_type="e_string" />
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<efx:param name="auto_instantiation" value="off" value_type="e_bool" />
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<efx:param name="profile" value="NONE" value_type="e_string" />
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</efx:debugger>
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</efx:project>
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@@ -1,31 +0,0 @@
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ca65 V2.19 - Git 71b58f796
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Main file : main.s
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Current file: main.s
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000000r 1 .export _init, _nmi_int, _irq_int
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000000r 1
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000000r 1
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000000r 1 SDRAM = $200
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000000r 1
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000000r 1 .segment "VECTORS"
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000000r 1
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000000r 1 rr rr .addr _nmi_int ; NMI vector
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000002r 1 rr rr .addr _init ; Reset vector
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000004r 1 rr rr .addr _irq_int ; IRQ/BRK vector
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000006r 1
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000006r 1 .code
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000000r 1
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000000r 1 _nmi_int:
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000000r 1 _irq_int:
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000000r 1
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000000r 1 _init:
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000000r 1 A9 00 lda #$00
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000002r 1 @start:
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000002r 1 8D 00 02 sta SDRAM
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000005r 1 CD 00 02 cmp SDRAM
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000008r 1 D0 03 bne @end
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00000Ar 1 1A ina
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00000Br 1 80 F5 bra @start
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00000Dr 1
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00000Dr 1 80 FE @end: bra @end
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00000Dr 1
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Binary file not shown.
@@ -1,28 +0,0 @@
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Modules list:
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-------------
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main.o:
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CODE Offs=000000 Size=00000F Align=00001 Fill=0000
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VECTORS Offs=000000 Size=000006 Align=00001 Fill=0000
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Segment list:
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-------------
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Name Start End Size Align
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----------------------------------------------------
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CODE 00FF00 00FF0E 00000F 00001
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VECTORS 00FFFA 00FFFF 000006 00001
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Exports list by name:
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---------------------
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Exports list by value:
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----------------------
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Imports list:
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-------------
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