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Add basic sim

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This commit is contained in:
Byron Lathi
2024-03-03 17:06:10 -08:00
parent ab9da189d1
commit 01b1ecbcac
9 changed files with 152 additions and 1 deletions
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3
hw/super6502_fpga/src/sim/sources.list Normal file
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hvl/sim_top.sv
sub/verilog-6502/ALU.v
sub/verilog-6502/cpu_65c02.v