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Add basic project with cpu, ram and rom

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Byron Lathi
2024-03-02 22:46:48 -08:00
parent 0a0394ae33
commit 0752220b0e
15 changed files with 1019 additions and 0 deletions
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hw/super6502_fpga/Makefile Normal file
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SUPER6502_FPGA_SOURCES=$(shell cat sources.list)
SUPER6502_FPGA_BITSTREAM=outflow/super6502_fpga.hex
SUPER6502_FPGA_PROJECT=super6502_fpga.xml
all: $(SUPER6502_FPGA_BITSTREAM)
$(SUPER6502_FPGA_BITSTREAM): $(SUPER6502_FPGA_SOURCES) $(SUPER6502_FPGA_PROJECT)
efx_run.py $(SUPER6502_FPGA_PROJECT)
.PHONY: clean
clean:
rm -rf work_*
rm -rf outflow