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Byron Lathi
2024-03-02 20:10:50 -08:00
parent 273484b994
commit 0a0394ae33
293 changed files with 1 additions and 94765 deletions
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228
.gitlab-ci.yml
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# This file is a template, and might need editing before it works on your project.
# This is a sample GitLab CI/CD configuration file that should run without any modifications.
# It demonstrates a basic 3 stage CI/CD pipeline. Instead of real tests or scripts,
# it uses echo commands to simulate the pipeline execution.
#
# A pipeline is composed of independent jobs that run scripts, grouped into stages.
# Stages run in sequential order, but jobs within stages run in parallel.
#
# For more information, see: https://docs.gitlab.com/ee/ci/yaml/index.html#stages
#
# You can copy and paste this template into a new `.gitlab-ci.yml` file.
# You should not add this template to an existing `.gitlab-ci.yml` file by using the `include:` keyword.
#
# To contribute improvements to CI/CD templates, please follow the Development guide at:
# https://docs.gitlab.com/ee/development/cicd/templates.html
# This specific template is located at:
# https://gitlab.com/gitlab-org/gitlab/-/blob/master/lib/gitlab/ci/templates/Getting-Started.gitlab-ci.yml
variables:
GIT_SUBMODULE_PATHS: ":(exclude)hw/kicad_library"
GIT_SUBMODULE_STRATEGY: recursive
stages: # List of stages for jobs, and their order of execution
- toolchain
- build_sw
- build_hw
- simulate
build toolchain:
retry: 2
tags:
- linux
stage: toolchain
script:
- source init_env.sh
- cd sw/cc65
- make -j 12
artifacts:
paths:
- sw/cc65/bin
- sw/cc65/lib
build bios:
tags:
- linux
stage: build_sw
needs:
- job: build toolchain
artifacts: true
artifacts:
paths:
- hw/efinix_fpga/init_hex.mem
script:
- source init_env.sh
- cd sw/
- make bios
build kernel:
tags:
- linux
stage: build_sw
needs:
- job: build toolchain
artifacts: true
script:
- source init_env.sh
- cd sw/
- make kernel
build fpga: # This job runs in the build stage, which runs first.
tags:
- efinity
- linux
stage: build_hw
needs:
- job: build bios
artifacts: true
script:
- source init_env.sh
- cd hw/efinix_fpga
- make
full sim:
when: manual
tags:
- linux
- iverilog
stage: simulate
artifacts:
paths:
- hw/efinix_fpga/simulation/sim_top.vcd
- hw/efinix_fpga/simulation/fs.fat
script:
- source init_env.sh
- cd hw/efinix_fpga/simulation
- make clean
- TEST_PROGRAM=$REPO_TOP/sw/bios/bios.hex TEST_FOLDER=$REPO_TOP/sw/bios make full_sim
needs:
- job: build toolchain
artifacts: true
- job: build bios
artifacts: true
- job: build kernel
artifacts: true
mapper sim:
tags:
- linux
- iverilog
stage: simulate
needs:
- job: build toolchain
artifacts: true
artifacts:
paths:
- hw/efinix_fpga/simulation/mapper_tb.vcd
script:
- source init_env.sh
- cd hw/efinix_fpga/simulation
- make clean
- make mapper_tb
- ./mapper_tb
mapper_code sim:
tags:
- linux
- iverilog
stage: simulate
needs:
- job: build toolchain
artifacts: true
artifacts:
paths:
- hw/efinix_fpga/simulation/mapper_code_tb.vcd
script:
- source init_env.sh
- cd hw/efinix_fpga/simulation
- make clean
- TEST_PROGRAM_NAME=mapper_test make mapper_code_tb
- ./mapper_code_tb
multiplier_code sim:
tags:
- linux
- iverilog
stage: simulate
needs:
- job: build toolchain
artifacts: true
artifacts:
paths:
- hw/efinix_fpga/simulation/mapper_code_tb.vcd
script:
- source init_env.sh
- cd hw/efinix_fpga/simulation
- make clean
- TEST_PROGRAM_NAME=multiplier_test make mapper_code_tb
- ./mapper_code_tb
interrupt_controller sim:
tags:
- linux
- iverilog
stage: simulate
needs:
- job: build toolchain
artifacts: true
artifacts:
paths:
- hw/efinix_fpga/simulation/interrupt_controller.vcd
script:
- source init_env.sh
- cd hw/efinix_fpga/simulation
- make clean
- TEST_PROGRAM_NAME=mapper_test make interrupt_controller_tb
- ./interrupt_controller_tb
interrupt_controller_code sim:
tags:
- linux
- iverilog
stage: simulate
needs:
- job: build toolchain
artifacts: true
artifacts:
paths:
- hw/efinix_fpga/simulation/interrupt_controller_code.vcd
script:
- source init_env.sh
- cd hw/efinix_fpga/simulation
- make clean
- TEST_PROGRAM_NAME=mapper_test make interrupt_controller_code_tb
- ./interrupt_controller_code_tb
rtc_code sim:
tags:
- linux
- iverilog
stage: simulate
needs:
- job: build toolchain
artifacts: true
artifacts:
paths:
- hw/efinix_fpga/simulation/interrupt_controller_code.vcd
script:
- source init_env.sh
- cd hw/efinix_fpga/simulation
- make clean
- TEST_PROGRAM_NAME=rtc_test make rtc_code_tb
- ./rtc_code_tb
devices_setup_code sim:
tags:
- linux
- iverilog
stage: simulate
needs:
- job: build toolchain
artifacts: true
script:
- source init_env.sh
- cd hw/efinix_fpga/simulation
- make clean
- TEST_PROGRAM_NAME=devices_setup_test make devices_setup_code_tb
- ./devices_setup_code_tb

12
.gitmodules vendored
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[submodule "sw/cc65"]
path = sw/cc65
url = https://git.byronlathi.com/bslathi19/cc65
[submodule "hw/efinix_fpga/simulation/src/verilog-6502"]
path = hw/efinix_fpga/simulation/src/verilog-6502
url = https://git.byronlathi.com/bslathi19/verilog-6502
[submodule "hw/efinix_fpga/simulation/src/verilog-sd-emulator"]
path = hw/efinix_fpga/simulation/src/verilog-sd-emulator
url = https://git.byronlathi.com/bslathi19/verilog-sd-emulator
[submodule "hw/kicad_library"]
path = hw/kicad_library
url = https://git.byronlathi.com/bslathi19/kicad_library.git

41
README.md
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@@ -27,46 +27,7 @@ Along the way, there are a few milestones that I want to reach:
* HDMI Display output
* Ethernet
## Details
Currently, the project is built around an Efinix Trion T20F256 Development board.
I also have a breakout board with an SD card slot, a MAX3421E, and an audio codec
(that I forget the pn) which I got at school. Right now I only use the SD card.
The development board is sparse, but it includes SDRAM and enough headers to add
any other peripherals.
I designed a board to plug into one of the headers which exposes nearly all the pins
of a 65C02 directly to the FPGA, with no external circuitry except for 2 pull-up
resistors.
The heart of the project is `super6502.sv`. This file contains all of the various
parts of the project. It contains a small boot rom, but the rest of the code is
loaded from an SD card. All of the peripherals are also instantiated here, and there
is a block at the top for address decoding. It currently contains a very simple MMU
which allows the CPU access to the full 32MB address space. Other peripherals include
a timer, leds, hardware multiplier and divider, a uart, an spi controller (for the sd
card), an interrupt controller, and the SDRAM controller.
The SDRAM controller is the one supplied by the FPGA manufacturer, efinix, but contained
in a wrapper which adapts the native bus to the 6502 bus.
One aspect of the project that I want to improve on is bus interoperability. There is
a huge world of IP that is available if I support AXI or WishBone, but at the moment
I do not.
## Simulation Effort
Because I mostly work on this project while on the bus going to/from work, I can't be
iteratively testing on the hardware. I was inspired by the simulation setup we have at
work for the Starlink ASICs and decided to try and implement something similar, albeit
with only free tools at my disposal. It mostly works, but is very slow. Booting the
kernel takes nearly an hour(!), and that is with no kernel features or functionality.
For this reason, the IP blocks have standalone simulations as well as full system
simulations
## Contributing
While I appreciate feedback, this my own personal project and I will not accept
external contributions.
external contributions.

293
doc/memory_mapper/memory_mapper.drawio
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# Memory Mapper
## Overview
The memory mapper gives expands the CPU's address space from 16 bits to 25.
It can be expanded to be 28 bits, but only 25 are needed to access all of
sdram.
Its architecture is show below:
![memory_mapper.drawio.png](memory_mapper.drawio.png)
There are 32 16 bit registers: One for each 4k page in the virtual address
space. The memory mapper is always enabled, but at reset it is identity
mapped, i.e. register _n_ will be reset to value _n_.
## Interface
The Memory mapper is composed of 32 identical 16 bit mapping registers
The chip select should be calculated based on the virtual address. If not,
it will be possible for the CPU to map away access to the mapper, at which
point it is impossible to change the mappings without a reset.
## Registers
### Register Map
| Address | Read | Write |
|--------- |-------------- |-------------- |
| 00 | MM0 Low | MM0 Low |
| 01 | MM0 High | MM0 High |
| 02 | MM1 Low | MM1 Low |
| 03 | MM1 High | MM1 High |
| 04 | MM2 Low | MM2 Low |
| 05 | MM2 High | MM2 High |
| 06 | MM3 Low | MM3 Low |
| 07 | MM3 High | MM3 High |
| 08 | MM4 Low | MM4 Low |
| 09 | MM4 High | MM4 High |
| 0A | MM5 Low | MM5 Low |
| 0B | MM5 High | MM5 High |
| 0C | MM6 Low | MM6 Low |
| 0D | MM6 High | MM6 High |
| 0E | MM7 Low | MM7 Low |
| 0F | MM7 High | MM7 High |
| 10 | MM8 Low | MM8 Low |
| 11 | MM8 High | MM8 High |
| 12 | MM9 Low | MM9 Low |
| 13 | MM9 High | MM9 High |
| 14 | MM10 Low | MM10 Low |
| 15 | MM10 High | MM10 High |
| 16 | MM11 Low | MM11 Low |
| 17 | MM11 High | MM11 High |
| 18 | MM12 Low | MM12 Low |
| 19 | MM12 High | MM12 High |
| 1A | MM13 Low | MM13 Low |
| 1B | MM13 High | MM13 High |
| 1C | MM14 Low | MM14 Low |
| 1D | MM14 High | MM14 High |
| 1E | MM15 Low | MM15 Low |
| 1F | MM15 High | MM15 High |
### MMn Low
Low memory map data. Becomes bits [19:12] of physical address.
### MMn High
High memory map data. Becomes bits [27:20] of physical address.

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# PIC
## Overview
The PIC (Programmable Interrupt Controller) supports 256 edge or level
triggered interrupts.
Interrupts can only be rising edge or positive level trigger. Negative edge or
low level trigger can be accomplished by inverting the input to this module.
When an interrupt is triggered, it remains triggered until cleared with an
`EOI`. Currently, only the highest priority interrupt can be cleared. This
is bad design and will be fixed soon(tm).
![pic.drawio.png](pic.drawio.png)
## Interface
The PIC is controlled through two 8-bit registers, `CMD` and `DAT`.
The upepr 3 bits of `CMD` control which register is accessed, and the lower 5
bits control the byte select.
`EOI` is a special case: when `CMD` is 0xFF, the highest priority interrupt is
cleared.
### CMD
| [7:5] | [4:0] |
|------------------ |------------- |
| Register Address | Byte Select |
### DAT
| [7:0] |
|----------------------- |
| Data[8*Byte_sel +: 8] |
## Registers
### Register Map
| Address | Read | Write |
|--------- |------------ |-------- |
| 0 | IRQ Number | ~ |
| 1 | Enable | Enable |
| 2 | Type | Type |
### IRQ Number
8 bit register outputs the highest priority interrupt currently active. When
no interrupt is active, it will output 255.
### Enable
256 bit enable register. When bit _n_ is set to 1, the corresponding interrupt
_n_.
### Type
256 bit type register. When bit _n_ is set to 0, the corresponding interrupt
_n_ will be edge triggered. If the bit is set to 1, the interrupt will be level
triggered.

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# RTC
## Overview
The RTC is capable of keeping track of elapsed time as well as generating
periodic interrupts. Its input frequency is (currently) the same as the CPU
frequency. The architecture is shown below:
![rtc.drawio.png](rtc.drawio.png)
The `counter` register is a 32 bit register which increments by `increment`
every clock tick. When this value reaches `threshold`, both `output` and
`irq_counter` are incremented by 1. When `irq_counter` reaches `irq_threshold`,
an interrupt is generated.
The interrupt frequency can be calculated with the following equations:
$$ F_{out}=\frac{F_{in}\cdot{increment}}{threshold} $$
$$ F_{irq}=\frac{F_{out}}{irq\_threshold} $$
Where $ F_{out} $ is the frequency at which the output changes and $ F_{irq} $
is the frequency at which interrupts occur.
## Interface
The RTC is controlled through two 8-bit registers, `CMD` and `DAT`.
The upepr 4 bits of `CMD` control which register is accessed, and the lower 4
bits control the byte select. The RTC uses 32 bit registers, so only values of
0-3 are supported.
### CMD
| [7:4] | [3:2 | [1:0] |
|------------------ |---------- |------------- |
| Register Address | Reserved | Byte Select |
### DAT
| [7:0] |
|----------------------- |
| Data[8*Byte_sel +: 8] |
## Registers
### Register Map
| Address | Read | Write |
|--------- |--------------- |--------------- |
| 0 | Threshold | Threshold |
| 1 | Increment | Increment |
| 2 | IRQ Threshold | IRQ Threshold |
| 3 | Output | Control |
### Threshold
32 bit threshold register. When `counter` reaches this value, `output` and
`irq_counter` are incremented by 1, and `counter` is reset back to 0.
### Increment
32 bit increment register. Every clock cycle, `counter` is incremented by
`increment`
### IRQ Threshold
32 bit IRQ threshold register. When `irq_counter` reaches this value, and IRQ
is generated and `irq_counter` is reset back to 0.
### Output
32 bit output register. This value ticks up.
### Control
| [7:2] | [1] | [0] |
|---------- |------------ |-------- |
| Reserved | IRQ Enable | Enable |
8 bit Control register. Regardless of Byte Select, any write to address 3 will
write to this register. `IRQ Enable` controls interrupt generation. `Enable` is
a global enable. When 0, all counter registers are set to 0.

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31
hw/385_adapter/.gitignore vendored
View File

@@ -1,31 +0,0 @@
# For PCBs designed using KiCad: https://www.kicad.org/
# Format documentation: https://kicad.org/help/file-formats/
# Temporary files
*.000
*.bak
*.bck
*.kicad_pcb-bak
*.kicad_sch-bak
*-backups
*.kicad_prl
*.sch-bak
*~
_autosave-*
*.tmp
*-save.pro
*-save.kicad_pcb
fp-info-cache
# Netlist files (exported from Eeschema)
*.net
# Autorouter files (exported from Pcbnew)
*.dsn
*.ses
# Exported BOM files
*.xml
*.csv
gerbers*

6204
hw/385_adapter/385_adapter.kicad_pcb
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File diff suppressed because it is too large Load Diff

420
hw/385_adapter/385_adapter.kicad_pro
View File

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{
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"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
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"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
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"version": 1
},
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"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
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"meta": {
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},
"pcbnew": {
"last_paths": {
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"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
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},
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"meta": {
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"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
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],
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}

1862
hw/385_adapter/385_adapter.kicad_sch
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File diff suppressed because it is too large Load Diff

30
hw/board/.gitignore vendored
View File

@@ -1,30 +0,0 @@
# Temporary files
*.000
*.bak
*.bck
*.kicad_pcb-bak
*.kicad_sch-bak
*.kicad_prl
*.sch-bak
*~
_autosave-*
*.tmp
*-save.pro
*-save.kicad_pcb
fp-info-cache
# Netlist files (exported from Eeschema)
*.net
# Autorouter files (exported from Pcbnew)
*.dsn
*.ses
# Exported BOM files
*.xml
*.csv
# kicad 8 backups
*-backups
output/
output*

6026
hw/board/board/board.kicad_pcb
View File

File diff suppressed because it is too large Load Diff

517
hw/board/board/board.kicad_pro
View File

@@ -1,517 +0,0 @@
{
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330
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936
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hw/board/board/ddr.kicad_sch
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654
hw/board/board/ethernet.kicad_sch
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143
hw/board/board/fp-lib-table
View File

@@ -1,143 +0,0 @@
(fp_lib_table
(version 7)
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(lib (name "Battery")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Battery.pretty")(options "")(descr ""))
(lib (name "Button_Switch_Keyboard")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Button_Switch_Keyboard.pretty")(options "")(descr ""))
(lib (name "Button_Switch_SMD")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Button_Switch_SMD.pretty")(options "")(descr ""))
(lib (name "Button_Switch_THT")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Button_Switch_THT.pretty")(options "")(descr ""))
(lib (name "Buzzer_Beeper")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Buzzer_Beeper.pretty")(options "")(descr ""))
(lib (name "Calibration_Scale")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Calibration_Scale.pretty")(options "")(descr ""))
(lib (name "Capacitor_SMD")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Capacitor_SMD.pretty")(options "")(descr ""))
(lib (name "Capacitor_Tantalum_SMD")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Capacitor_Tantalum_SMD.pretty")(options "")(descr ""))
(lib (name "Capacitor_THT")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Capacitor_THT.pretty")(options "")(descr ""))
(lib (name "Connector")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector.pretty")(options "")(descr ""))
(lib (name "Connector_AMASS")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_AMASS.pretty")(options "")(descr ""))
(lib (name "Connector_Amphenol")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Amphenol.pretty")(options "")(descr ""))
(lib (name "Connector_Audio")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Audio.pretty")(options "")(descr ""))
(lib (name "Connector_BarrelJack")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_BarrelJack.pretty")(options "")(descr ""))
(lib (name "Connector_Card")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Card.pretty")(options "")(descr ""))
(lib (name "Connector_Coaxial")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Coaxial.pretty")(options "")(descr ""))
(lib (name "Connector_DIN")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_DIN.pretty")(options "")(descr ""))
(lib (name "Connector_Dsub")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Dsub.pretty")(options "")(descr ""))
(lib (name "Connector_FFC-FPC")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_FFC-FPC.pretty")(options "")(descr ""))
(lib (name "Connector_Harting")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Harting.pretty")(options "")(descr ""))
(lib (name "Connector_Harwin")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Harwin.pretty")(options "")(descr ""))
(lib (name "Connector_HDMI")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_HDMI.pretty")(options "")(descr ""))
(lib (name "Connector_Hirose")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Hirose.pretty")(options "")(descr ""))
(lib (name "Connector_IDC")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_IDC.pretty")(options "")(descr ""))
(lib (name "Connector_JAE")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_JAE.pretty")(options "")(descr ""))
(lib (name "Connector_JST")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_JST.pretty")(options "")(descr ""))
(lib (name "Connector_Molex")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Molex.pretty")(options "")(descr ""))
(lib (name "Connector_Murata")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Murata.pretty")(options "")(descr ""))
(lib (name "Connector_PCBEdge")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_PCBEdge.pretty")(options "")(descr ""))
(lib (name "Connector_Phoenix_GMSTB")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Phoenix_GMSTB.pretty")(options "")(descr ""))
(lib (name "Connector_Phoenix_MC")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Phoenix_MC.pretty")(options "")(descr ""))
(lib (name "Connector_Phoenix_MC_HighVoltage")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Phoenix_MC_HighVoltage.pretty")(options "")(descr ""))
(lib (name "Connector_Phoenix_MSTB")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Phoenix_MSTB.pretty")(options "")(descr ""))
(lib (name "Connector_Pin")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Pin.pretty")(options "")(descr ""))
(lib (name "Connector_PinHeader_1.00mm")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_PinHeader_1.00mm.pretty")(options "")(descr ""))
(lib (name "Connector_PinHeader_1.27mm")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_PinHeader_1.27mm.pretty")(options "")(descr ""))
(lib (name "Connector_PinHeader_2.00mm")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_PinHeader_2.00mm.pretty")(options "")(descr ""))
(lib (name "Connector_PinHeader_2.54mm")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_PinHeader_2.54mm.pretty")(options "")(descr ""))
(lib (name "Connector_PinSocket_1.00mm")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_PinSocket_1.00mm.pretty")(options "")(descr ""))
(lib (name "Connector_PinSocket_1.27mm")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_PinSocket_1.27mm.pretty")(options "")(descr ""))
(lib (name "Connector_PinSocket_2.00mm")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_PinSocket_2.00mm.pretty")(options "")(descr ""))
(lib (name "Connector_PinSocket_2.54mm")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_PinSocket_2.54mm.pretty")(options "")(descr ""))
(lib (name "Connector_RJ")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_RJ.pretty")(options "")(descr ""))
(lib (name "Connector_Samtec")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Samtec.pretty")(options "")(descr ""))
(lib (name "Connector_Samtec_HLE_SMD")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Samtec_HLE_SMD.pretty")(options "")(descr ""))
(lib (name "Connector_Samtec_HLE_THT")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Samtec_HLE_THT.pretty")(options "")(descr ""))
(lib (name "Connector_SATA_SAS")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_SATA_SAS.pretty")(options "")(descr ""))
(lib (name "Connector_Stocko")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Stocko.pretty")(options "")(descr ""))
(lib (name "Connector_TE-Connectivity")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_TE-Connectivity.pretty")(options "")(descr ""))
(lib (name "Connector_USB")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_USB.pretty")(options "")(descr ""))
(lib (name "Connector_Wago")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Wago.pretty")(options "")(descr ""))
(lib (name "Connector_Wire")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Wire.pretty")(options "")(descr ""))
(lib (name "Connector_Wuerth")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Connector_Wuerth.pretty")(options "")(descr ""))
(lib (name "Converter_ACDC")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Converter_ACDC.pretty")(options "")(descr ""))
(lib (name "Converter_DCDC")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Converter_DCDC.pretty")(options "")(descr ""))
(lib (name "Crystal")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Crystal.pretty")(options "")(descr ""))
(lib (name "Diode_SMD")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Diode_SMD.pretty")(options "")(descr ""))
(lib (name "Diode_THT")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Diode_THT.pretty")(options "")(descr ""))
(lib (name "Display")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Display.pretty")(options "")(descr ""))
(lib (name "Display_7Segment")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Display_7Segment.pretty")(options "")(descr ""))
(lib (name "Ferrite_THT")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Ferrite_THT.pretty")(options "")(descr ""))
(lib (name "Fiducial")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Fiducial.pretty")(options "")(descr ""))
(lib (name "Filter")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Filter.pretty")(options "")(descr ""))
(lib (name "Fuse")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Fuse.pretty")(options "")(descr ""))
(lib (name "Heatsink")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Heatsink.pretty")(options "")(descr ""))
(lib (name "Inductor_SMD")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Inductor_SMD.pretty")(options "")(descr ""))
(lib (name "Inductor_THT")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Inductor_THT.pretty")(options "")(descr ""))
(lib (name "Jumper")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Jumper.pretty")(options "")(descr ""))
(lib (name "LED_SMD")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/LED_SMD.pretty")(options "")(descr ""))
(lib (name "LED_THT")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/LED_THT.pretty")(options "")(descr ""))
(lib (name "Module")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Module.pretty")(options "")(descr ""))
(lib (name "MountingEquipment")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/MountingEquipment.pretty")(options "")(descr ""))
(lib (name "MountingHole")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/MountingHole.pretty")(options "")(descr ""))
(lib (name "Mounting_Wuerth")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Mounting_Wuerth.pretty")(options "")(descr ""))
(lib (name "NetTie")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/NetTie.pretty")(options "")(descr ""))
(lib (name "OptoDevice")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/OptoDevice.pretty")(options "")(descr ""))
(lib (name "Oscillator")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Oscillator.pretty")(options "")(descr ""))
(lib (name "Package_BGA")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Package_BGA.pretty")(options "")(descr ""))
(lib (name "Package_CSP")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Package_CSP.pretty")(options "")(descr ""))
(lib (name "Package_DFN_QFN")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Package_DFN_QFN.pretty")(options "")(descr ""))
(lib (name "Package_DIP")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Package_DIP.pretty")(options "")(descr ""))
(lib (name "Package_DirectFET")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Package_DirectFET.pretty")(options "")(descr ""))
(lib (name "Package_LCC")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Package_LCC.pretty")(options "")(descr ""))
(lib (name "Package_LGA")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Package_LGA.pretty")(options "")(descr ""))
(lib (name "Package_QFP")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Package_QFP.pretty")(options "")(descr ""))
(lib (name "Package_SC")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Package_SC.pretty")(options "")(descr ""))
(lib (name "Package_SIP")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Package_SIP.pretty")(options "")(descr ""))
(lib (name "Package_SO")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Package_SO.pretty")(options "")(descr ""))
(lib (name "Package_SO_J-Lead")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Package_SO_J-Lead.pretty")(options "")(descr ""))
(lib (name "Package_SON")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Package_SON.pretty")(options "")(descr ""))
(lib (name "Package_TO_SOT_SMD")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Package_TO_SOT_SMD.pretty")(options "")(descr ""))
(lib (name "Package_TO_SOT_THT")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Package_TO_SOT_THT.pretty")(options "")(descr ""))
(lib (name "Package_TSNP")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Package_TSNP.pretty")(options "")(descr ""))
(lib (name "Potentiometer_SMD")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Potentiometer_SMD.pretty")(options "")(descr ""))
(lib (name "Potentiometer_THT")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Potentiometer_THT.pretty")(options "")(descr ""))
(lib (name "Relay_SMD")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Relay_SMD.pretty")(options "")(descr ""))
(lib (name "Relay_THT")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Relay_THT.pretty")(options "")(descr ""))
(lib (name "Resistor_SMD")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Resistor_SMD.pretty")(options "")(descr ""))
(lib (name "Resistor_THT")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Resistor_THT.pretty")(options "")(descr ""))
(lib (name "RF")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/RF.pretty")(options "")(descr ""))
(lib (name "RF_Antenna")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/RF_Antenna.pretty")(options "")(descr ""))
(lib (name "RF_Converter")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/RF_Converter.pretty")(options "")(descr ""))
(lib (name "RF_GPS")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/RF_GPS.pretty")(options "")(descr ""))
(lib (name "RF_GSM")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/RF_GSM.pretty")(options "")(descr ""))
(lib (name "RF_Mini-Circuits")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/RF_Mini-Circuits.pretty")(options "")(descr ""))
(lib (name "RF_Module")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/RF_Module.pretty")(options "")(descr ""))
(lib (name "RF_Shielding")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/RF_Shielding.pretty")(options "")(descr ""))
(lib (name "RF_WiFi")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/RF_WiFi.pretty")(options "")(descr ""))
(lib (name "Rotary_Encoder")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Rotary_Encoder.pretty")(options "")(descr ""))
(lib (name "Sensor")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Sensor.pretty")(options "")(descr ""))
(lib (name "Sensor_Audio")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Sensor_Audio.pretty")(options "")(descr ""))
(lib (name "Sensor_Current")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Sensor_Current.pretty")(options "")(descr ""))
(lib (name "Sensor_Distance")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Sensor_Distance.pretty")(options "")(descr ""))
(lib (name "Sensor_Humidity")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Sensor_Humidity.pretty")(options "")(descr ""))
(lib (name "Sensor_Motion")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Sensor_Motion.pretty")(options "")(descr ""))
(lib (name "Sensor_Pressure")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Sensor_Pressure.pretty")(options "")(descr ""))
(lib (name "Sensor_Voltage")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Sensor_Voltage.pretty")(options "")(descr ""))
(lib (name "Socket")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Socket.pretty")(options "")(descr ""))
(lib (name "ST")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/ST.pretty")(options "")(descr ""))
(lib (name "Symbol")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Symbol.pretty")(options "")(descr ""))
(lib (name "TerminalBlock")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/TerminalBlock.pretty")(options "")(descr ""))
(lib (name "TerminalBlock_4Ucon")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/TerminalBlock_4Ucon.pretty")(options "")(descr ""))
(lib (name "TerminalBlock_Altech")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/TerminalBlock_Altech.pretty")(options "")(descr ""))
(lib (name "TerminalBlock_Dinkle")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/TerminalBlock_Dinkle.pretty")(options "")(descr ""))
(lib (name "TerminalBlock_MetzConnect")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/TerminalBlock_MetzConnect.pretty")(options "")(descr ""))
(lib (name "TerminalBlock_Philmore")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/TerminalBlock_Philmore.pretty")(options "")(descr ""))
(lib (name "TerminalBlock_Phoenix")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/TerminalBlock_Phoenix.pretty")(options "")(descr ""))
(lib (name "TerminalBlock_RND")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/TerminalBlock_RND.pretty")(options "")(descr ""))
(lib (name "TerminalBlock_TE-Connectivity")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/TerminalBlock_TE-Connectivity.pretty")(options "")(descr ""))
(lib (name "TerminalBlock_WAGO")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/TerminalBlock_WAGO.pretty")(options "")(descr ""))
(lib (name "TerminalBlock_Wuerth")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/TerminalBlock_Wuerth.pretty")(options "")(descr ""))
(lib (name "TestPoint")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/TestPoint.pretty")(options "")(descr ""))
(lib (name "Transformer_SMD")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Transformer_SMD.pretty")(options "")(descr ""))
(lib (name "Transformer_THT")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Transformer_THT.pretty")(options "")(descr ""))
(lib (name "Transistor_Power_Module")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Transistor_Power_Module.pretty")(options "")(descr ""))
(lib (name "Valve")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Valve.pretty")(options "")(descr ""))
(lib (name "Varistor")(type "KiCad")(uri "${KICAD7_FOOTPRINT_DIR}/Varistor.pretty")(options "")(descr ""))
)

7331
hw/board/board/fpga.kicad_sch
View File

File diff suppressed because it is too large Load Diff

643
hw/board/board/ftdi.kicad_sch
View File

@@ -1,643 +0,0 @@
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209
hw/board/board/hdmi.kicad_sch
View File

@@ -1,209 +0,0 @@
(kicad_sch (version 20230121) (generator eeschema)
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3320
hw/board/board/power.kicad_sch
View File

File diff suppressed because it is too large Load Diff

213
hw/board/board/sym-lib-table
View File

@@ -1,213 +0,0 @@
(sym_lib_table
(version 7)
(lib (name "4xxx")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/4xxx.kicad_sym")(options "")(descr ""))
(lib (name "4xxx_IEEE")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/4xxx_IEEE.kicad_sym")(options "")(descr ""))
(lib (name "74xGxx")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/74xGxx.kicad_sym")(options "")(descr ""))
(lib (name "74xx")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/74xx.kicad_sym")(options "")(descr ""))
(lib (name "74xx_IEEE")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/74xx_IEEE.kicad_sym")(options "")(descr ""))
(lib (name "Amplifier_Audio")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Amplifier_Audio.kicad_sym")(options "")(descr ""))
(lib (name "Amplifier_Buffer")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Amplifier_Buffer.kicad_sym")(options "")(descr ""))
(lib (name "Amplifier_Current")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Amplifier_Current.kicad_sym")(options "")(descr ""))
(lib (name "Amplifier_Difference")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Amplifier_Difference.kicad_sym")(options "")(descr ""))
(lib (name "Amplifier_Instrumentation")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Amplifier_Instrumentation.kicad_sym")(options "")(descr ""))
(lib (name "Amplifier_Operational")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Amplifier_Operational.kicad_sym")(options "")(descr ""))
(lib (name "Amplifier_Video")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Amplifier_Video.kicad_sym")(options "")(descr ""))
(lib (name "Analog")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Analog.kicad_sym")(options "")(descr ""))
(lib (name "Analog_ADC")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Analog_ADC.kicad_sym")(options "")(descr ""))
(lib (name "Analog_DAC")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Analog_DAC.kicad_sym")(options "")(descr ""))
(lib (name "Analog_Switch")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Analog_Switch.kicad_sym")(options "")(descr ""))
(lib (name "Antenna")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Antenna.kicad_sym")(options "")(descr ""))
(lib (name "arduino")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/arduino.kicad_sym")(options "")(descr ""))
(lib (name "Audio")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Audio.kicad_sym")(options "")(descr ""))
(lib (name "Battery_Management")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Battery_Management.kicad_sym")(options "")(descr ""))
(lib (name "Buffer")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Buffer.kicad_sym")(options "")(descr ""))
(lib (name "Comparator")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Comparator.kicad_sym")(options "")(descr ""))
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(lib (name "Connector_Generic")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Connector_Generic.kicad_sym")(options "")(descr ""))
(lib (name "Connector_Generic_MountingPin")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Connector_Generic_MountingPin.kicad_sym")(options "")(descr ""))
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(lib (name "Conn_Murata")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Conn_Murata.kicad_sym")(options "")(descr ""))
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(lib (name "Converter_DCDC")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Converter_DCDC.kicad_sym")(options "")(descr ""))
(lib (name "CPLD_Altera")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/CPLD_Altera.kicad_sym")(options "")(descr ""))
(lib (name "CPLD_Microchip")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/CPLD_Microchip.kicad_sym")(options "")(descr ""))
(lib (name "CPLD_Xilinx")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/CPLD_Xilinx.kicad_sym")(options "")(descr ""))
(lib (name "CPU")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/CPU.kicad_sym")(options "")(descr ""))
(lib (name "CPU_NXP_6800")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/CPU_NXP_6800.kicad_sym")(options "")(descr ""))
(lib (name "CPU_NXP_68000")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/CPU_NXP_68000.kicad_sym")(options "")(descr ""))
(lib (name "CPU_NXP_IMX")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/CPU_NXP_IMX.kicad_sym")(options "")(descr ""))
(lib (name "CPU_PowerPC")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/CPU_PowerPC.kicad_sym")(options "")(descr ""))
(lib (name "Device")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Device.kicad_sym")(options "")(descr ""))
(lib (name "Diode")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Diode.kicad_sym")(options "")(descr ""))
(lib (name "Diode_Bridge")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Diode_Bridge.kicad_sym")(options "")(descr ""))
(lib (name "Diode_Laser")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Diode_Laser.kicad_sym")(options "")(descr ""))
(lib (name "Display_Character")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Display_Character.kicad_sym")(options "")(descr ""))
(lib (name "Display_Graphic")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Display_Graphic.kicad_sym")(options "")(descr ""))
(lib (name "Driver_Display")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Driver_Display.kicad_sym")(options "")(descr ""))
(lib (name "Driver_FET")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Driver_FET.kicad_sym")(options "")(descr ""))
(lib (name "Driver_Haptic")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Driver_Haptic.kicad_sym")(options "")(descr ""))
(lib (name "Driver_LED")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Driver_LED.kicad_sym")(options "")(descr ""))
(lib (name "Driver_Motor")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Driver_Motor.kicad_sym")(options "")(descr ""))
(lib (name "Driver_Relay")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Driver_Relay.kicad_sym")(options "")(descr ""))
(lib (name "Driver_TEC")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Driver_TEC.kicad_sym")(options "")(descr ""))
(lib (name "DSP_AnalogDevices")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/DSP_AnalogDevices.kicad_sym")(options "")(descr ""))
(lib (name "DSP_Freescale")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/DSP_Freescale.kicad_sym")(options "")(descr ""))
(lib (name "DSP_Microchip_DSPIC33")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/DSP_Microchip_DSPIC33.kicad_sym")(options "")(descr ""))
(lib (name "DSP_Motorola")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/DSP_Motorola.kicad_sym")(options "")(descr ""))
(lib (name "DSP_Texas")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/DSP_Texas.kicad_sym")(options "")(descr ""))
(lib (name "Fiber_Optic")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Fiber_Optic.kicad_sym")(options "")(descr ""))
(lib (name "Filter")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Filter.kicad_sym")(options "")(descr ""))
(lib (name "FPGA_Lattice")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/FPGA_Lattice.kicad_sym")(options "")(descr ""))
(lib (name "FPGA_Microsemi")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/FPGA_Microsemi.kicad_sym")(options "")(descr ""))
(lib (name "FPGA_Xilinx")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/FPGA_Xilinx.kicad_sym")(options "")(descr ""))
(lib (name "FPGA_Xilinx_Artix7")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/FPGA_Xilinx_Artix7.kicad_sym")(options "")(descr ""))
(lib (name "FPGA_Xilinx_Kintex7")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/FPGA_Xilinx_Kintex7.kicad_sym")(options "")(descr ""))
(lib (name "FPGA_Xilinx_Spartan6")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/FPGA_Xilinx_Spartan6.kicad_sym")(options "")(descr ""))
(lib (name "FPGA_Xilinx_Virtex5")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/FPGA_Xilinx_Virtex5.kicad_sym")(options "")(descr ""))
(lib (name "FPGA_Xilinx_Virtex6")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/FPGA_Xilinx_Virtex6.kicad_sym")(options "")(descr ""))
(lib (name "FPGA_Xilinx_Virtex7")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/FPGA_Xilinx_Virtex7.kicad_sym")(options "")(descr ""))
(lib (name "GPU")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/GPU.kicad_sym")(options "")(descr ""))
(lib (name "Graphic")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Graphic.kicad_sym")(options "")(descr ""))
(lib (name "Header")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Header.kicad_sym")(options "")(descr ""))
(lib (name "IC")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/IC.kicad_sym")(options "")(descr ""))
(lib (name "Interface")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Interface.kicad_sym")(options "")(descr ""))
(lib (name "Interface_CAN_LIN")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Interface_CAN_LIN.kicad_sym")(options "")(descr ""))
(lib (name "Interface_CurrentLoop")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Interface_CurrentLoop.kicad_sym")(options "")(descr ""))
(lib (name "Interface_Ethernet")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Interface_Ethernet.kicad_sym")(options "")(descr ""))
(lib (name "Interface_Expansion")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Interface_Expansion.kicad_sym")(options "")(descr ""))
(lib (name "Interface_HDMI")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Interface_HDMI.kicad_sym")(options "")(descr ""))
(lib (name "Interface_HID")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Interface_HID.kicad_sym")(options "")(descr ""))
(lib (name "Interface_LineDriver")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Interface_LineDriver.kicad_sym")(options "")(descr ""))
(lib (name "Interface_Optical")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Interface_Optical.kicad_sym")(options "")(descr ""))
(lib (name "Interface_Telecom")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Interface_Telecom.kicad_sym")(options "")(descr ""))
(lib (name "Interface_UART")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Interface_UART.kicad_sym")(options "")(descr ""))
(lib (name "Interface_USB")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Interface_USB.kicad_sym")(options "")(descr ""))
(lib (name "Isolator")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Isolator.kicad_sym")(options "")(descr ""))
(lib (name "Isolator_Analog")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Isolator_Analog.kicad_sym")(options "")(descr ""))
(lib (name "Jumper")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Jumper.kicad_sym")(options "")(descr ""))
(lib (name "LED")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/LED.kicad_sym")(options "")(descr ""))
(lib (name "Logic_LevelTranslator")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Logic_LevelTranslator.kicad_sym")(options "")(descr ""))
(lib (name "Logic_Programmable")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Logic_Programmable.kicad_sym")(options "")(descr ""))
(lib (name "MCU_AnalogDevices")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_AnalogDevices.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Cypress")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Cypress.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Dialog")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Dialog.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Espressif")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Espressif.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Intel")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Intel.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Microchip_8051")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Microchip_8051.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Microchip_ATmega")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Microchip_ATmega.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Microchip_ATtiny")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Microchip_ATtiny.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Microchip_AVR")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Microchip_AVR.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Microchip_PIC10")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Microchip_PIC10.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Microchip_PIC12")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Microchip_PIC12.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Microchip_PIC16")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Microchip_PIC16.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Microchip_PIC18")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Microchip_PIC18.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Microchip_PIC24")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Microchip_PIC24.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Microchip_PIC32")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Microchip_PIC32.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Microchip_SAMA")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Microchip_SAMA.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Microchip_SAMD")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Microchip_SAMD.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Microchip_SAME")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Microchip_SAME.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Microchip_SAML")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Microchip_SAML.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Microchip_SAMV")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Microchip_SAMV.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Module")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Module.kicad_sym")(options "")(descr ""))
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(lib (name "MCU_NXP_ColdFire")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_NXP_ColdFire.kicad_sym")(options "")(descr ""))
(lib (name "MCU_NXP_HC11")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_NXP_HC11.kicad_sym")(options "")(descr ""))
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(lib (name "MCU_NXP_HCS12")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_NXP_HCS12.kicad_sym")(options "")(descr ""))
(lib (name "MCU_NXP_Kinetis")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_NXP_Kinetis.kicad_sym")(options "")(descr ""))
(lib (name "MCU_NXP_LPC")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_NXP_LPC.kicad_sym")(options "")(descr ""))
(lib (name "MCU_NXP_MAC7100")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_NXP_MAC7100.kicad_sym")(options "")(descr ""))
(lib (name "MCU_NXP_MCore")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_NXP_MCore.kicad_sym")(options "")(descr ""))
(lib (name "MCU_NXP_NTAG")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_NXP_NTAG.kicad_sym")(options "")(descr ""))
(lib (name "MCU_NXP_S08")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_NXP_S08.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Parallax")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Parallax.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Renesas_Synergy_S1")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Renesas_Synergy_S1.kicad_sym")(options "")(descr ""))
(lib (name "MCU_SiFive")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_SiFive.kicad_sym")(options "")(descr ""))
(lib (name "MCU_SiliconLabs")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_SiliconLabs.kicad_sym")(options "")(descr ""))
(lib (name "MCU_STC")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_STC.kicad_sym")(options "")(descr ""))
(lib (name "MCU_ST_STM8")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_ST_STM8.kicad_sym")(options "")(descr ""))
(lib (name "MCU_ST_STM32F0")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_ST_STM32F0.kicad_sym")(options "")(descr ""))
(lib (name "MCU_ST_STM32F1")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_ST_STM32F1.kicad_sym")(options "")(descr ""))
(lib (name "MCU_ST_STM32F2")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_ST_STM32F2.kicad_sym")(options "")(descr ""))
(lib (name "MCU_ST_STM32F3")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_ST_STM32F3.kicad_sym")(options "")(descr ""))
(lib (name "MCU_ST_STM32F4")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_ST_STM32F4.kicad_sym")(options "")(descr ""))
(lib (name "MCU_ST_STM32F7")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_ST_STM32F7.kicad_sym")(options "")(descr ""))
(lib (name "MCU_ST_STM32G0")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_ST_STM32G0.kicad_sym")(options "")(descr ""))
(lib (name "MCU_ST_STM32H7")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_ST_STM32H7.kicad_sym")(options "")(descr ""))
(lib (name "MCU_ST_STM32L0")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_ST_STM32L0.kicad_sym")(options "")(descr ""))
(lib (name "MCU_ST_STM32L1")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_ST_STM32L1.kicad_sym")(options "")(descr ""))
(lib (name "MCU_ST_STM32L4")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_ST_STM32L4.kicad_sym")(options "")(descr ""))
(lib (name "MCU_ST_STM32L4+")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_ST_STM32L4+.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Texas")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Texas.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Texas_MSP430")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Texas_MSP430.kicad_sym")(options "")(descr ""))
(lib (name "MCU_Texas_SimpleLink")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/MCU_Texas_SimpleLink.kicad_sym")(options "")(descr ""))
(lib (name "Mechanical")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Mechanical.kicad_sym")(options "")(descr ""))
(lib (name "Memory_EEPROM")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Memory_EEPROM.kicad_sym")(options "")(descr ""))
(lib (name "Memory_EPROM")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Memory_EPROM.kicad_sym")(options "")(descr ""))
(lib (name "Memory_Flash")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Memory_Flash.kicad_sym")(options "")(descr ""))
(lib (name "Memory_NVRAM")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Memory_NVRAM.kicad_sym")(options "")(descr ""))
(lib (name "Memory_RAM")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Memory_RAM.kicad_sym")(options "")(descr ""))
(lib (name "Memory_ROM")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Memory_ROM.kicad_sym")(options "")(descr ""))
(lib (name "Memory_UniqueID")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Memory_UniqueID.kicad_sym")(options "")(descr ""))
(lib (name "Motor")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Motor.kicad_sym")(options "")(descr ""))
(lib (name "Oscillator")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Oscillator.kicad_sym")(options "")(descr ""))
(lib (name "Potentiometer_Digital")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Potentiometer_Digital.kicad_sym")(options "")(descr ""))
(lib (name "power")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/power.kicad_sym")(options "")(descr ""))
(lib (name "Power_Management")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Power_Management.kicad_sym")(options "")(descr ""))
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(lib (name "Power_Supervisor")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Power_Supervisor.kicad_sym")(options "")(descr ""))
(lib (name "pspice")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/pspice.kicad_sym")(options "")(descr ""))
(lib (name "Reference_Current")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Reference_Current.kicad_sym")(options "")(descr ""))
(lib (name "Reference_Voltage")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Reference_Voltage.kicad_sym")(options "")(descr ""))
(lib (name "Regulator_Controller")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Regulator_Controller.kicad_sym")(options "")(descr ""))
(lib (name "Regulator_Current")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Regulator_Current.kicad_sym")(options "")(descr ""))
(lib (name "Regulator_Linear")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Regulator_Linear.kicad_sym")(options "")(descr ""))
(lib (name "Regulator_SwitchedCapacitor")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Regulator_SwitchedCapacitor.kicad_sym")(options "")(descr ""))
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(lib (name "Relay")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Relay.kicad_sym")(options "")(descr ""))
(lib (name "Relay_SolidState")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Relay_SolidState.kicad_sym")(options "")(descr ""))
(lib (name "RF")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/RF.kicad_sym")(options "")(descr ""))
(lib (name "RF_AM_FM")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/RF_AM_FM.kicad_sym")(options "")(descr ""))
(lib (name "RF_Amplifier")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/RF_Amplifier.kicad_sym")(options "")(descr ""))
(lib (name "RF_Bluetooth")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/RF_Bluetooth.kicad_sym")(options "")(descr ""))
(lib (name "RF_Filter")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/RF_Filter.kicad_sym")(options "")(descr ""))
(lib (name "RF_GPS")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/RF_GPS.kicad_sym")(options "")(descr ""))
(lib (name "RF_GSM")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/RF_GSM.kicad_sym")(options "")(descr ""))
(lib (name "RF_Mixer")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/RF_Mixer.kicad_sym")(options "")(descr ""))
(lib (name "RF_Module")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/RF_Module.kicad_sym")(options "")(descr ""))
(lib (name "RF_NFC")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/RF_NFC.kicad_sym")(options "")(descr ""))
(lib (name "RF_RFID")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/RF_RFID.kicad_sym")(options "")(descr ""))
(lib (name "RF_Switch")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/RF_Switch.kicad_sym")(options "")(descr ""))
(lib (name "RF_WiFi")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/RF_WiFi.kicad_sym")(options "")(descr ""))
(lib (name "RF_ZigBee")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/RF_ZigBee.kicad_sym")(options "")(descr ""))
(lib (name "Security")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Security.kicad_sym")(options "")(descr ""))
(lib (name "Sensor")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Sensor.kicad_sym")(options "")(descr ""))
(lib (name "Sensor_Audio")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Sensor_Audio.kicad_sym")(options "")(descr ""))
(lib (name "Sensor_Current")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Sensor_Current.kicad_sym")(options "")(descr ""))
(lib (name "Sensor_Distance")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Sensor_Distance.kicad_sym")(options "")(descr ""))
(lib (name "Sensor_Gas")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Sensor_Gas.kicad_sym")(options "")(descr ""))
(lib (name "Sensor_Humidity")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Sensor_Humidity.kicad_sym")(options "")(descr ""))
(lib (name "Sensor_Magnetic")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Sensor_Magnetic.kicad_sym")(options "")(descr ""))
(lib (name "Sensor_Motion")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Sensor_Motion.kicad_sym")(options "")(descr ""))
(lib (name "Sensor_Optical")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Sensor_Optical.kicad_sym")(options "")(descr ""))
(lib (name "Sensor_Pressure")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Sensor_Pressure.kicad_sym")(options "")(descr ""))
(lib (name "Sensor_Proximity")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Sensor_Proximity.kicad_sym")(options "")(descr ""))
(lib (name "Sensor_Temperature")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Sensor_Temperature.kicad_sym")(options "")(descr ""))
(lib (name "Sensor_Touch")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Sensor_Touch.kicad_sym")(options "")(descr ""))
(lib (name "Sensor_Voltage")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Sensor_Voltage.kicad_sym")(options "")(descr ""))
(lib (name "Simulation_SPICE")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Simulation_SPICE.kicad_sym")(options "")(descr ""))
(lib (name "ST")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/ST.kicad_sym")(options "")(descr ""))
(lib (name "Switch")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Switch.kicad_sym")(options "")(descr ""))
(lib (name "Timer")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Timer.kicad_sym")(options "")(descr ""))
(lib (name "Timer_PLL")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Timer_PLL.kicad_sym")(options "")(descr ""))
(lib (name "Timer_RTC")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Timer_RTC.kicad_sym")(options "")(descr ""))
(lib (name "Transformer")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Transformer.kicad_sym")(options "")(descr ""))
(lib (name "Transistor_Array")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Transistor_Array.kicad_sym")(options "")(descr ""))
(lib (name "Transistor_BJT")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Transistor_BJT.kicad_sym")(options "")(descr ""))
(lib (name "Transistor_FET")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Transistor_FET.kicad_sym")(options "")(descr ""))
(lib (name "Transistor_IGBT")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Transistor_IGBT.kicad_sym")(options "")(descr ""))
(lib (name "Transistor_Power_Module")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Transistor_Power_Module.kicad_sym")(options "")(descr ""))
(lib (name "Triac_Thyristor")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Triac_Thyristor.kicad_sym")(options "")(descr ""))
(lib (name "Valve")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Valve.kicad_sym")(options "")(descr ""))
(lib (name "Video")(type "KiCad")(uri "${KICAD7_SYMBOL_DIR}/Video.kicad_sym")(options "")(descr ""))
)

652
hw/board/board/usb.kicad_sch
View File

@@ -1,652 +0,0 @@
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252
hw/board/board/vga.kicad_sch
View File

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1
hw/board/docs/.gitattributes vendored
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3
hw/board/docs/10029449.pdf
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# For PCBs designed using KiCad: https://www.kicad.org/
# Format documentation: https://kicad.org/help/file-formats/
# Temporary files
*.000
*.bak
*.bck
*.kicad_pcb-bak
*.kicad_sch-bak
*-backups
*.kicad_prl
*.sch-bak
*~
_autosave-*
*.tmp
*-save.pro
*-save.kicad_pcb
fp-info-cache
# Netlist files (exported from Eeschema)
*.net
# Autorouter files (exported from Pcbnew)
*.dsn
*.ses
# Exported BOM files
*.xml
*.csv
gerbers*

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{
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"defaults": {
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},
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"boards": [],
"cvpcb": {
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"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
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},
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"pinned_symbol_libs": []
},
"meta": {
"filename": "efinix_adapter.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
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"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
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"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
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"via_drill": 0.4,
"wire_width": 6.0
}
],
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},
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},
"pcbnew": {
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"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
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},
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"drawing": {
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"junction_size_choice": 3,
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"pin_symbol_size": 25.0,
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},
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"legacy_lib_list": [],
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"ngspice": {
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"workbook_filename": ""
},
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"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
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},
"sheets": [
[
"74bfc30e-6eb9-47c0-9164-e4166fb40ecb",
""
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10
hw/efinix_fpga/.gitignore vendored
View File

@@ -1,10 +0,0 @@
work_*
.lock
outflow
*.vdb
*.log*
*.vcd
*.gtkw
*.vvp
*.mem

21
hw/efinix_fpga/Makefile
View File

@@ -1,21 +0,0 @@
PROJECT=super6502
BITSTREAM=outflow/$(PROJECT).bit
SRCS=$(shell find src/ -type f -name "*.sv")
all: $(BITSTREAM)
$(BITSTREAM): $(PROJECT).peri.xml $(SRCS)
efx_run.py $(PROJECT).xml
install: $(BITSTREAM)
efx_run.py $(PROJECT).xml --flow program --pgm_opts mode=jtag
install_spi: $(BITSTREAM)
efx_run.py $(PROJECT).xml --flow program --pgm_opts
clean:
rm -rf work_pnr
rm -rf work_syn
rm -rf work_pt
rm -rf outflow

284
hw/efinix_fpga/constraints/super6502.pt.sdc
View File

@@ -1,284 +0,0 @@
# Efinity Interface Designer SDC
# Version: 2022.1.226
# Date: 2022-12-21 23:10
# Copyright (C) 2017 - 2022 Efinix Inc. All rights reserved.
# Device: T20F256
# Project: super6502
# Timing Model: C4 (final)
# PLL Constraints
#################
create_clock -period 20.0000 clk_50
create_generated_clock -source clk_50 -multiply_by 4 i_sdrclk
create_generated_clock -source clk_50 -multiply_by 4 i_tACclk
create_generated_clock -source clk_50 -multiply_by 2 i_sysclk
create_generated_clock -source clk_50 -divide_by 25 clk_cpu
# create_clock -period 5.0000 i_sdrclk
# create_clock -period 5.0000 i_tACclk
# create_clock -period 10.0000 i_sysclk
# create_clock -period 500.0000 clk_cpu
# GPIO Constraints
####################
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {button_reset}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {button_reset}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[0]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[0]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[1]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[1]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[2]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[2]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[3]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[3]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[4]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[4]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[5]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[5]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[6]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[6]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[7]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[7]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[8]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[8]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[9]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[9]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[10]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[10]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[11]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[11]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[12]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[12]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[13]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[13]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[14]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[14]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_addr[15]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_addr[15]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_rwb}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_rwb}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_sync}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_sync}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {pll_in}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {pll_in}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_phi2}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_phi2}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_irqb}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_irqb}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_nmib}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_nmib}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_rdy}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_rdy}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_resb}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_resb}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {leds[0]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {leds[0]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {leds[1]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {leds[1]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {leds[2]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {leds[2]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {leds[3]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {leds[3]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {leds[4]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {leds[4]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {leds[5]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {leds[5]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {leds[6]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {leds[6]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {leds[7]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {leds[7]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[0]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[0]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[1]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[1]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[2]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[2]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[3]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[3]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[4]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[4]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[5]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[5]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[6]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[6]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[7]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[7]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[8]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[8]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[9]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[9]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[10]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[10]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[11]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[11]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_ADDR[12]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_ADDR[12]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_BA[0]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_BA[0]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_BA[1]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_BA[1]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_CK}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_CK}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_CKE}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_CKE}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DQM[0]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DQM[0]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DQM[1]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DQM[1]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_n_CAS}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_n_CAS}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_n_CS}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_n_CS}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_n_RAS}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_n_RAS}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_n_WE}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_n_WE}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[0]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[0]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[0]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[0]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[0]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[0]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[1]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[1]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[1]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[1]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[1]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[1]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[2]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[2]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[2]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[2]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[2]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[2]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[3]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[3]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[3]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[3]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[3]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[3]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[4]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[4]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[4]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[4]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[4]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[4]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[5]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[5]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[5]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[5]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[5]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[5]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[6]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[6]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[6]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[6]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[6]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[6]}]
# set_input_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_in[7]}]
# set_input_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_in[7]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_out[7]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_out[7]}]
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {cpu_data_oe[7]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {cpu_data_oe[7]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[0]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[0]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[0]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[0]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[0]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[0]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[1]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[1]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[1]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[1]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[1]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[1]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[2]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[2]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[2]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[2]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[2]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[2]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[3]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[3]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[3]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[3]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[3]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[3]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[4]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[4]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[4]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[4]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[4]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[4]}]
set_input_delay -clock i_sdrclk -max 5.768 [get_ports {i_sdr_DATA[5]}]
set_input_delay -clock i_sdrclk -min 2.884 [get_ports {i_sdr_DATA[5]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[5]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[5]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[5]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[5]}]
set_input_delay -clock i_sdrclk -max 5.568 [get_ports {i_sdr_DATA[6]}]
set_input_delay -clock i_sdrclk -min 2.784 [get_ports {i_sdr_DATA[6]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[6]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[6]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[6]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[6]}]
set_input_delay -clock i_sdrclk -max 5.768 [get_ports {i_sdr_DATA[7]}]
set_input_delay -clock i_sdrclk -min 2.884 [get_ports {i_sdr_DATA[7]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[7]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[7]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[7]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[7]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[8]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[8]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[8]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[8]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[8]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[8]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[9]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[9]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[9]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[9]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[9]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[9]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[10]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[10]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[10]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[10]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[10]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[10]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[11]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[11]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[11]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[11]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[11]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[11]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[12]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[12]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[12]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[12]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[12]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[12]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[13]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[13]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[13]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[13]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[13]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[13]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[14]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[14]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[14]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[14]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[14]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[14]}]
set_input_delay -clock i_sdrclk -max 4.968 [get_ports {i_sdr_DATA[15]}]
set_input_delay -clock i_sdrclk -min 2.484 [get_ports {i_sdr_DATA[15]}]
set_output_delay -clock i_sdrclk -max -3.500 [get_ports {o_sdr_DATA[15]}]
set_output_delay -clock i_sdrclk -min -2.139 [get_ports {o_sdr_DATA[15]}]
set_output_delay -clock i_sdrclk -max -3.507 [get_ports {o_sdr_DATA_oe[15]}]
set_output_delay -clock i_sdrclk -min -2.143 [get_ports {o_sdr_DATA_oe[15]}]

510
hw/efinix_fpga/debug_profile.wizard.json
View File

@@ -1,510 +0,0 @@
{
"debug_cores": [
{
"name": "la0",
"type": "la",
"uuid": "426fe3342997403e8dbac6dd07d86e1e",
"trigin_en": false,
"trigout_en": false,
"auto_inserted": true,
"capture_control": false,
"data_depth": 8192,
"input_pipeline": 1,
"probes": [
{
"name": "cpu_data_in",
"width": 8,
"probe_type": 1
},
{
"name": "cpu_rwb",
"width": 1,
"probe_type": 1
},
{
"name": "cpu_addr",
"width": 16,
"probe_type": 1
},
{
"name": "cpu_sync",
"width": 1,
"probe_type": 1
},
{
"name": "cpu_rdy",
"width": 1,
"probe_type": 1
},
{
"name": "w_sdram_addr",
"width": 25,
"probe_type": 1
}
]
}
],
"connections": [
{
"command": "add_ports",
"id": 1,
"args": {
"netlist": "super6502",
"ports": [
{
"name": "jtag_inst1_CAPTURE",
"dir": "in",
"width": 1
},
{
"name": "jtag_inst1_DRCK",
"dir": "in",
"width": 1
},
{
"name": "jtag_inst1_RESET",
"dir": "in",
"width": 1
},
{
"name": "jtag_inst1_RUNTEST",
"dir": "in",
"width": 1
},
{
"name": "jtag_inst1_SEL",
"dir": "in",
"width": 1
},
{
"name": "jtag_inst1_SHIFT",
"dir": "in",
"width": 1
},
{
"name": "jtag_inst1_TCK",
"dir": "in",
"width": 1
},
{
"name": "jtag_inst1_TDI",
"dir": "in",
"width": 1
},
{
"name": "jtag_inst1_TMS",
"dir": "in",
"width": 1
},
{
"name": "jtag_inst1_UPDATE",
"dir": "in",
"width": 1
},
{
"name": "jtag_inst1_TDO",
"dir": "out",
"width": 1
}
]
}
},
{
"command": "instantiate",
"netlist": "edb_top",
"id": 2,
"instance": "edb_top_inst"
},
{
"command": "connect",
"id": 3,
"args": {
"instance": "edb_top_inst",
"ports": [
{
"name": "bscan_CAPTURE",
"net": "jtag_inst1_CAPTURE"
},
{
"name": "bscan_DRCK",
"net": "jtag_inst1_DRCK"
},
{
"name": "bscan_RESET",
"net": "jtag_inst1_RESET"
},
{
"name": "bscan_RUNTEST",
"net": "jtag_inst1_RUNTEST"
},
{
"name": "bscan_SEL",
"net": "jtag_inst1_SEL"
},
{
"name": "bscan_SHIFT",
"net": "jtag_inst1_SHIFT"
},
{
"name": "bscan_TCK",
"net": "jtag_inst1_TCK"
},
{
"name": "bscan_TDI",
"net": "jtag_inst1_TDI"
},
{
"name": "bscan_TMS",
"net": "jtag_inst1_TMS"
},
{
"name": "bscan_UPDATE",
"net": "jtag_inst1_UPDATE"
},
{
"name": "bscan_TDO",
"net": "jtag_inst1_TDO"
},
{
"name": "la0_clk",
"net": "clk_2",
"path": []
},
{
"name": "la0_probe0[0]",
"net": "cpu_data_in[0]",
"path": []
},
{
"name": "la0_probe0[1]",
"net": "cpu_data_in[1]",
"path": []
},
{
"name": "la0_probe0[2]",
"net": "cpu_data_in[2]",
"path": []
},
{
"name": "la0_probe0[3]",
"net": "cpu_data_in[3]",
"path": []
},
{
"name": "la0_probe0[4]",
"net": "cpu_data_in[4]",
"path": []
},
{
"name": "la0_probe0[5]",
"net": "cpu_data_in[5]",
"path": []
},
{
"name": "la0_probe0[6]",
"net": "cpu_data_in[6]",
"path": []
},
{
"name": "la0_probe0[7]",
"net": "cpu_data_in[7]",
"path": []
},
{
"name": "la0_probe1",
"net": "cpu_rwb",
"path": []
},
{
"name": "la0_probe2[0]",
"net": "cpu_addr[0]",
"path": []
},
{
"name": "la0_probe2[1]",
"net": "cpu_addr[1]",
"path": []
},
{
"name": "la0_probe2[2]",
"net": "cpu_addr[2]",
"path": []
},
{
"name": "la0_probe2[3]",
"net": "cpu_addr[3]",
"path": []
},
{
"name": "la0_probe2[4]",
"net": "cpu_addr[4]",
"path": []
},
{
"name": "la0_probe2[5]",
"net": "cpu_addr[5]",
"path": []
},
{
"name": "la0_probe2[6]",
"net": "cpu_addr[6]",
"path": []
},
{
"name": "la0_probe2[7]",
"net": "cpu_addr[7]",
"path": []
},
{
"name": "la0_probe2[8]",
"net": "cpu_addr[8]",
"path": []
},
{
"name": "la0_probe2[9]",
"net": "cpu_addr[9]",
"path": []
},
{
"name": "la0_probe2[10]",
"net": "cpu_addr[10]",
"path": []
},
{
"name": "la0_probe2[11]",
"net": "cpu_addr[11]",
"path": []
},
{
"name": "la0_probe2[12]",
"net": "cpu_addr[12]",
"path": []
},
{
"name": "la0_probe2[13]",
"net": "cpu_addr[13]",
"path": []
},
{
"name": "la0_probe2[14]",
"net": "cpu_addr[14]",
"path": []
},
{
"name": "la0_probe2[15]",
"net": "cpu_addr[15]",
"path": []
},
{
"name": "la0_probe3",
"net": "cpu_sync",
"path": []
},
{
"name": "la0_probe4",
"net": "cpu_rdy",
"path": []
},
{
"name": "la0_probe5[0]",
"net": "w_sdram_addr[0]",
"path": []
},
{
"name": "la0_probe5[1]",
"net": "w_sdram_addr[1]",
"path": []
},
{
"name": "la0_probe5[2]",
"net": "w_sdram_addr[2]",
"path": []
},
{
"name": "la0_probe5[3]",
"net": "w_sdram_addr[3]",
"path": []
},
{
"name": "la0_probe5[4]",
"net": "w_sdram_addr[4]",
"path": []
},
{
"name": "la0_probe5[5]",
"net": "w_sdram_addr[5]",
"path": []
},
{
"name": "la0_probe5[6]",
"net": "w_sdram_addr[6]",
"path": []
},
{
"name": "la0_probe5[7]",
"net": "w_sdram_addr[7]",
"path": []
},
{
"name": "la0_probe5[8]",
"net": "w_sdram_addr[8]",
"path": []
},
{
"name": "la0_probe5[9]",
"net": "w_sdram_addr[9]",
"path": []
},
{
"name": "la0_probe5[10]",
"net": "w_sdram_addr[10]",
"path": []
},
{
"name": "la0_probe5[11]",
"net": "w_sdram_addr[11]",
"path": []
},
{
"name": "la0_probe5[12]",
"net": "w_sdram_addr[12]",
"path": []
},
{
"name": "la0_probe5[13]",
"net": "w_sdram_addr[13]",
"path": []
},
{
"name": "la0_probe5[14]",
"net": "w_sdram_addr[14]",
"path": []
},
{
"name": "la0_probe5[15]",
"net": "w_sdram_addr[15]",
"path": []
},
{
"name": "la0_probe5[16]",
"net": "w_sdram_addr[16]",
"path": []
},
{
"name": "la0_probe5[17]",
"net": "w_sdram_addr[17]",
"path": []
},
{
"name": "la0_probe5[18]",
"net": "w_sdram_addr[18]",
"path": []
},
{
"name": "la0_probe5[19]",
"net": "w_sdram_addr[19]",
"path": []
},
{
"name": "la0_probe5[20]",
"net": "w_sdram_addr[20]",
"path": []
},
{
"name": "la0_probe5[21]",
"net": "w_sdram_addr[21]",
"path": []
},
{
"name": "la0_probe5[22]",
"net": "w_sdram_addr[22]",
"path": []
},
{
"name": "la0_probe5[23]",
"net": "w_sdram_addr[23]",
"path": []
},
{
"name": "la0_probe5[24]",
"net": "w_sdram_addr[24]",
"path": []
}
]
}
}
],
"vdbs": [
{
"file": "debug_top.post.vdb",
"instance": "edb_top_inst"
}
],
"session": {
"wizard": {
"data_depth": 8192,
"capture_control": false,
"selected_nets": [
{
"name": "cpu_data_in",
"width": 8,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": [],
"net_idx_left": 7,
"net_idx_right": 0
},
{
"name": "cpu_rwb",
"width": 1,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": []
},
{
"name": "cpu_addr",
"width": 16,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": [],
"net_idx_left": 15,
"net_idx_right": 0
},
{
"name": "cpu_sync",
"width": 1,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": []
},
{
"name": "cpu_rdy",
"width": 1,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": []
},
{
"name": "w_sdram_addr",
"width": 25,
"clk_domain": "clk_2",
"selected_probe_type": "DATA AND TRIGGER",
"child": [],
"path": [],
"net_idx_left": 24,
"net_idx_right": 0
}
],
"top_module": "super6502",
"db_checksum": "ba5fce12098a2c03e7bae2e9a172d1842464edfca8e284870b3519e987537970",
"src": "elaborate",
"jtag_user": "USER1",
"input_pipeline": 1
}
}
}

390
hw/efinix_fpga/ip/divider/divider.v
View File

@@ -1,390 +0,0 @@
// =============================================================================
// Generated by efx_ipmgr
// Version: 2023.1.150
// IP Version: 5.0
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
`define IP_UUID _80fa5e3b79ce4c76a6cd48724ad5bdd2
`define IP_NAME_CONCAT(a,b) a``b
`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID)
module divider (
input [15:0] numer,
input [15:0] denom,
input clken,
input clk,
input reset,
output [15:0] quotient,
output [15:0] remain,
output rfd
);
`IP_MODULE_NAME(divider) #(
.NREPRESENTATION ("UNSIGNED"),
.WIDTHN (16),
.WIDTHD (16),
.DREPRESENTATION ("UNSIGNED"),
.PIPELINE (1'b0),
.LATENCY (16)
) u_divider(
.numer ( numer ),
.denom ( denom ),
.clken ( clken ),
.clk ( clk ),
.reset ( reset ),
.quotient ( quotient ),
.remain ( remain ),
.rfd ( rfd )
);
endmodule
`timescale 1ns / 1ps
module `IP_MODULE_NAME(divider) (
clk,
reset,
numer,
denom,
quotient,
remain,
rfd,
clken
);
parameter WIDTHN = 8;
parameter WIDTHD = 8;
parameter LATENCY = 8;
parameter PIPELINE = 1;
parameter NREPRESENTATION = "UNSIGNED";
parameter DREPRESENTATION = "UNSIGNED";
parameter ENABLE_OUTREG = 0;
input clk;
input reset;
input clken;
input [(WIDTHN-1):0] numer;
input [(WIDTHD-1):0] denom;
//output
output reg rfd;
output reg [(WIDTHN-1):0] quotient;
output reg [(WIDTHD-1):0] remain;
wire [WIDTHN-1:0] numer_temp;
wire [WIDTHD-1:0] denom_temp;
wire sign_numer;
wire sign_denom;
wire [(WIDTHN-1):0] quotient_copy;
wire [(WIDTHD-1):0] remain_copy;
reg sign_quotient[LATENCY:0];
genvar i, j;
// Main operation
generate begin
if(NREPRESENTATION == "SIGNED") begin
assign numer_temp = (numer[(WIDTHN-1)] == 1'b1) ? (~numer + 1) : numer;
assign sign_numer = (numer[(WIDTHN-1)] == 1'b1) ? 1'b1 : 1'b0;
end
else begin
assign numer_temp = numer;
assign sign_numer = 1'b0;
end
if(DREPRESENTATION == "SIGNED") begin
assign denom_temp = (denom[(WIDTHD-1)] == 1'b1) ? (~denom + 1) : denom;
assign sign_denom = (denom[(WIDTHD-1)] == 1'b1) ? 1'b1 : 1'b0;
end
else begin
assign denom_temp = denom;
assign sign_denom = 1'b0;
end
always @* begin
sign_quotient[0] = sign_numer ^ sign_denom;
end
for (i=0; i<LATENCY; i=i+1) begin
always @(posedge clk or posedge reset) begin
if (reset) begin
sign_quotient[i+1] <= 1'b0;
end
else if(clken) begin
sign_quotient[i+1] <= sign_quotient[i];
end
end
end
if (PIPELINE) begin : pipeline
wire [(WIDTHN+1):0] sub[WIDTHN-1:0];
reg [WIDTHN-1:0] quotient_temp[WIDTHN:0];
reg [WIDTHN-1:0] remain_temp[WIDTHN:0];
reg [WIDTHN-1:0] denom_copy[WIDTHN:0];
always @* begin
rfd = 1'b0; //for PIPELINE enable, rfd is not used
denom_copy[0] = denom_temp;
remain_temp[0] = {WIDTHN{1'b0}};
quotient_temp[0] = numer_temp;
end
for (i=0; i<WIDTHN; i=i+1) begin
assign sub[i] = {remain_temp[i][(WIDTHN-2):0], quotient_temp[i][(WIDTHN-1)]} - denom_copy[i];
if (i < LATENCY) begin
always @(posedge clk or posedge reset) begin
if (reset) begin
remain_temp[i+1] <= {WIDTHN{1'b0}};
quotient_temp[i+1] <= {WIDTHN{1'b0}};
denom_copy[i+1] <= {WIDTHN{1'b0}};
end
else if(clken) begin
denom_copy[i+1] <= denom_copy[i];
if (sub[i][(WIDTHN)] == 0) begin
remain_temp[i+1] <= sub[i][(WIDTHN-1):0];
quotient_temp[i+1] <= {quotient_temp[i][(WIDTHN-2):0], 1'b1};
end
else begin
remain_temp[i+1] <= {remain_temp[i][(WIDTHN-2):0], quotient_temp[i][(WIDTHN-1)]};
quotient_temp[i+1] <= {quotient_temp[i][(WIDTHN-2):0], 1'b0};
end
end
end
end
else begin
always @* begin
denom_copy[i+1] = denom_copy[i];
end
always @* begin
if (sub[i][(WIDTHN)] == 0) begin
remain_temp[i+1] = sub[i][(WIDTHN-1):0];
end
else begin
remain_temp[i+1] = {remain_temp[i][(WIDTHN-2):0], quotient_temp[i][(WIDTHN-1)]};
end
end
always @* begin
if (sub[i][(WIDTHN)] == 0) begin
quotient_temp[i+1] = {quotient_temp[i][(WIDTHN-2):0], 1'b1};
end
else begin
quotient_temp[i+1] = {quotient_temp[i][(WIDTHN-2):0], 1'b0};
end
end
end
end
if (NREPRESENTATION == "SIGNED" || DREPRESENTATION == "SIGNED") begin
assign quotient_copy = sign_quotient[LATENCY] ? (~quotient_temp[WIDTHN] + 1) : quotient_temp[WIDTHN];
end
else begin
assign quotient_copy = quotient_temp[WIDTHN];
end
assign remain_copy = remain_temp[WIDTHN];
end
else begin : non_pipeline
localparam COMBI_STAGE = WIDTHN - LATENCY;
wire [(WIDTHN-1):0] denom_sub;
reg [WIDTHN-1:0] denom_reg;
reg [(WIDTHN-1):0] quotient_reg;
reg [(WIDTHN-1):0] remain_reg;
wire [(WIDTHN+1):0] sub;
reg [(WIDTHN-1):0] quotient_combi[COMBI_STAGE:0];
reg [WIDTHN-1:0] remain_combi[COMBI_STAGE:0];
wire [(WIDTHN+1):0] sub_combi[COMBI_STAGE:0];
reg clken_IP;
assign denom_sub = {{(WIDTHN-WIDTHD){1'b0}},denom_temp};
always @(posedge clk,posedge reset) begin
if(reset) begin
clken_IP <= 1'b0;
end
else begin
clken_IP <= clken;
end
end
if(LATENCY > 0) begin
reg [LATENCY-1:0] ready;
assign sub = (ready[0] || ~clken_IP) ? ({{(WIDTHN-2){1'b0}}, numer_temp[(WIDTHN-1)]} - denom_sub) : ({remain_reg[(WIDTHN-2):0], quotient_reg[(WIDTHN-1)]} - denom_reg);
always @(posedge clk,posedge reset) begin
if(reset) begin
ready <= {LATENCY{1'b0}};
end
else if(clken) begin
if(ready[0] || ~clken_IP) begin
ready <= {1'b1, {LATENCY-1{1'b0}}};
end
else begin
ready <= {1'b0, ready[LATENCY-1:1]};
end
end
else begin
ready <= {LATENCY{1'b0}};
end
end
always @(posedge clk,posedge reset) begin
if(reset) begin
remain_reg <= {WIDTHN{1'b0}};
quotient_reg <= {WIDTHN{1'b0}};
denom_reg <= {WIDTHN{1'b0}};
end
else if(clken) begin
if(ready[0] || ~clken_IP) begin
denom_reg <= denom_temp;
if (sub[(WIDTHN)] == 0) begin
remain_reg <= sub[(WIDTHN-1):0];
quotient_reg <= {numer_temp[(WIDTHN-2):0], 1'b1};
end
else begin
remain_reg <= {{(WIDTHN-2){1'b0}}, numer_temp[(WIDTHN-1)]};
quotient_reg <= {numer_temp[(WIDTHN-2):0], 1'b0};
end
end
else begin
if (sub[(WIDTHN)] == 0) begin
remain_reg <= sub[(WIDTHN-1):0];
quotient_reg <= {quotient_reg[(WIDTHN-2):0], 1'b1};
end
else begin
remain_reg <= {remain_reg[(WIDTHN-2):0], quotient_reg[(WIDTHN-1)]};
quotient_reg <= {quotient_reg[(WIDTHN-2):0], 1'b0};
end
end
end
end
if (ENABLE_OUTREG) begin
always @(posedge clk,posedge reset) begin
if (reset) begin
rfd <= 1'b0;
end
else begin
rfd <= ready[0];
end
end
end
else begin
always @* begin
rfd = ready[0];
end
end
always @* begin
quotient_combi[0] = quotient_reg;
remain_combi[0] = remain_reg;
end
for (i=0; i<COMBI_STAGE; i=i+1) begin
assign sub_combi[i] = {remain_combi[i][(WIDTHN-2):0], quotient_combi[i][(WIDTHN-1)]} - denom_reg;
end
end
else begin
always @* begin
rfd = 1'b1;
end
always @* begin
quotient_combi[0] = numer_temp;
remain_combi[0] = {WIDTHN{1'b0}};
end
for (i=0; i<COMBI_STAGE; i=i+1) begin
assign sub_combi[i] = {remain_combi[i][(WIDTHN-2):0], quotient_combi[i][(WIDTHN-1)]} - denom_sub;
end
end
for (i=0; i<COMBI_STAGE; i=i+1) begin
always @* begin
if(sub_combi[i][(WIDTHN)] == 0) begin
remain_combi [i+1] = sub_combi[i][(WIDTHN-1):0];
quotient_combi [i+1] = {quotient_combi[i][(WIDTHN-2):0], 1'b1};
end
else begin
remain_combi[i+1] = {remain_combi[i][(WIDTHN-2):0], quotient_combi[i][(WIDTHN-1)]};
quotient_combi[i+1] = {quotient_combi[i][(WIDTHN-2):0], 1'b0};
end
end
end
if(NREPRESENTATION == "SIGNED" || DREPRESENTATION == "SIGNED") begin
assign quotient_copy = sign_quotient[LATENCY] ? (~quotient_combi[COMBI_STAGE] + 1): quotient_combi[COMBI_STAGE];//
end
else begin
assign quotient_copy = quotient_combi[COMBI_STAGE];
end
assign remain_copy = remain_combi[COMBI_STAGE];
end
if (ENABLE_OUTREG) begin
always @(posedge clk or posedge reset) begin
if (reset) begin
quotient <= {WIDTHN{1'b0}};
remain <= {WIDTHD{1'b0}};
end
else begin
quotient <= quotient_copy;
remain <= remain_copy;
end
end
end
else begin
always @* begin
quotient = quotient_copy;
remain = remain_copy;
end
end
end
endgenerate
endmodule
`undef IP_UUID
`undef IP_NAME_CONCAT
`undef IP_MODULE_NAME

51
hw/efinix_fpga/ip/divider/divider_define.vh
View File

@@ -1,51 +0,0 @@
// =============================================================================
// Generated by efx_ipmgr
// Version: 2023.1.150
// IP Version: 5.0
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
localparam NREPRESENTATION = "UNSIGNED";
localparam WIDTHN = 16;
localparam WIDTHD = 16;
localparam DREPRESENTATION = "UNSIGNED";
localparam PIPELINE = 1'b0;
localparam LATENCY = 16;

49
hw/efinix_fpga/ip/divider/divider_tmpl.v
View File

@@ -1,49 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
divider u_divider(
.numer ( numer ),
.denom ( denom ),
.clken ( clken ),
.clk ( clk ),
.reset ( reset ),
.quotient ( quotient ),
.remain ( remain ),
.rfd ( rfd )
);

64
hw/efinix_fpga/ip/divider/divider_tmpl.vhd
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@@ -1,64 +0,0 @@
--------------------------------------------------------------------------------
-- Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
--
-- This document contains proprietary information which is
-- protected by copyright. All rights are reserved. This notice
-- refers to original work by Efinix, Inc. which may be derivitive
-- of other work distributed under license of the authors. In the
-- case of derivative work, nothing in this notice overrides the
-- original author's license agreement. Where applicable, the
-- original license agreement is included in it's original
-- unmodified form immediately below this header.
--
-- WARRANTY DISCLAIMER.
-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
--
-- LIMITATION OF LIABILITY.
-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
-- APPLY TO LICENSEE.
--
--------------------------------------------------------------------------------
------------- Begin Cut here for COMPONENT Declaration ------
COMPONENT divider is
PORT (
numer : in std_logic_vector(15 downto 0);
denom : in std_logic_vector(15 downto 0);
clken : in std_logic;
clk : in std_logic;
reset : in std_logic;
quotient : out std_logic_vector(15 downto 0);
remain : out std_logic_vector(15 downto 0);
rfd : out std_logic);
END COMPONENT;
---------------------- End COMPONENT Declaration ------------
------------- Begin Cut here for INSTANTIATION Template -----
u_divider : divider
PORT MAP (
numer => numer,
denom => denom,
clken => clken,
clk => clk,
reset => reset,
quotient => quotient,
remain => remain,
rfd => rfd);
------------------------ End INSTANTIATION Template ---------

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{
"args": [
"-o",
"divider",
"--base_path",
"/tmp/tmpeltk99q_/ip",
"--vlnv",
{
"vendor": "efinixinc.com",
"library": "arithmetic",
"name": "efx_divider",
"version": "5.0"
}
],
"conf": {
"NREPRESENTATION": "\"UNSIGNED\"",
"WIDTHN": "16",
"WIDTHD": "16",
"DREPRESENTATION": "\"UNSIGNED\"",
"PIPELINE": "1'b0",
"LATENCY": "16"
},
"output": {
"external_source_source": [
"/tmp/tmpeltk99q_/ip/divider/divider_tmpl.vhd",
"/tmp/tmpeltk99q_/ip/divider/divider_define.vh",
"/tmp/tmpeltk99q_/ip/divider/divider_tmpl.v",
"/tmp/tmpeltk99q_/ip/divider/divider.v"
]
},
"sw_version": "2023.1.150",
"generated_date": "2023-07-16T16:45:12.554696"
}

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hw/efinix_fpga/ip/sdram_controller/sdram_controller.v
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hw/efinix_fpga/ip/sdram_controller/sdram_controller_define.vh
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// =============================================================================
// Generated by efx_ipmgr
// Version: 2023.1.150
// IP Version: 5.0
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
localparam fSYS_MHz = 100;
localparam fCK_MHz = 200;
localparam tIORT_u = 2;
localparam CL = 3;
localparam BL = 1;
localparam DDIO_TYPE = "SOFT";
localparam DQ_WIDTH = 8;
localparam DQ_GROUP = 2;
localparam BA_WIDTH = 2;
localparam ROW_WIDTH = 13;
localparam COL_WIDTH = 9;
localparam tPWRUP = 200000;
localparam tRAS = 44;
localparam tRAS_MAX = 120000;
localparam tRC = 66;
localparam tRCD = 20;
localparam tREF = 64000000;
localparam tRFC = 66;
localparam tRP = 20;
localparam tWR = 2;
localparam tMRD = 2;
localparam SDRAM_MODE = "Native";
localparam DATA_RATE = 2;
localparam AXI_AWADDR_WIDTH = 24;
localparam AXI_WDATA_WIDTH = 32;
localparam AXI_ARADDR_WIDTH = 24;
localparam AXI_RDATA_WIDTH = 32;
localparam AXI_AWID_WIDTH = 4;
localparam AXI_AWUSER_WIDTH = 2;
localparam AXI_WUSER_WIDTH = 2;
localparam AXI_BID_WIDTH = 4;
localparam AXI_BUSER_WIDTH = 2;
localparam AXI_ARID_WIDTH = 4;
localparam AXI_ARUSER_WIDTH = 3;
localparam AXI_RUSER_WIDTH = 3;

84
hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.v
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@@ -1,84 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
sdram_controller u_sdram_controller(
.i_we ( i_we ),
.i_sysclk ( i_sysclk ),
.i_arst ( i_arst ),
.i_sdrclk ( i_sdrclk ),
.i_tACclk ( i_tACclk ),
.i_pll_locked ( i_pll_locked ),
.i_re ( i_re ),
.i_last ( i_last ),
.o_dbg_tRTW_done ( o_dbg_tRTW_done ),
.o_dbg_ref_req ( o_dbg_ref_req ),
.o_dbg_wr_ack ( o_dbg_wr_ack ),
.o_dbg_rd_ack ( o_dbg_rd_ack ),
.o_dbg_n_CS ( o_dbg_n_CS ),
.o_dbg_n_RAS ( o_dbg_n_RAS ),
.o_dbg_n_CAS ( o_dbg_n_CAS ),
.o_dbg_n_WE ( o_dbg_n_WE ),
.o_dbg_BA ( o_dbg_BA ),
.o_dbg_ADDR ( o_dbg_ADDR ),
.o_dbg_DATA_out ( o_dbg_DATA_out ),
.o_dbg_DATA_in ( o_dbg_DATA_in ),
.i_addr ( i_addr ),
.i_din ( i_din ),
.i_dm ( i_dm ),
.o_dout ( o_dout ),
.o_sdr_state ( o_sdr_state ),
.o_sdr_init_done ( o_sdr_init_done ),
.o_wr_ack ( o_wr_ack ),
.o_rd_ack ( o_rd_ack ),
.o_ref_req ( o_ref_req ),
.o_rd_valid ( o_rd_valid ),
.o_sdr_CKE ( o_sdr_CKE ),
.o_sdr_n_CS ( o_sdr_n_CS ),
.o_sdr_n_RAS ( o_sdr_n_RAS ),
.o_sdr_n_CAS ( o_sdr_n_CAS ),
.o_sdr_n_WE ( o_sdr_n_WE ),
.o_sdr_BA ( o_sdr_BA ),
.o_sdr_ADDR ( o_sdr_ADDR ),
.o_sdr_DATA ( o_sdr_DATA ),
.o_sdr_DATA_oe ( o_sdr_DATA_oe ),
.i_sdr_DATA ( i_sdr_DATA ),
.o_sdr_DQM ( o_sdr_DQM ),
.o_dbg_dly_cnt_b ( o_dbg_dly_cnt_b ),
.o_dbg_tRCD_done ( o_dbg_tRCD_done )
);

134
hw/efinix_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd
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@@ -1,134 +0,0 @@
--------------------------------------------------------------------------------
-- Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
--
-- This document contains proprietary information which is
-- protected by copyright. All rights are reserved. This notice
-- refers to original work by Efinix, Inc. which may be derivitive
-- of other work distributed under license of the authors. In the
-- case of derivative work, nothing in this notice overrides the
-- original author's license agreement. Where applicable, the
-- original license agreement is included in it's original
-- unmodified form immediately below this header.
--
-- WARRANTY DISCLAIMER.
-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
--
-- LIMITATION OF LIABILITY.
-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
-- APPLY TO LICENSEE.
--
--------------------------------------------------------------------------------
------------- Begin Cut here for COMPONENT Declaration ------
COMPONENT sdram_controller is
PORT (
i_we : in std_logic;
i_sysclk : in std_logic;
i_arst : in std_logic;
i_sdrclk : in std_logic;
i_tACclk : in std_logic;
i_pll_locked : in std_logic;
i_re : in std_logic;
i_last : in std_logic;
o_dbg_tRTW_done : out std_logic;
o_dbg_ref_req : out std_logic;
o_dbg_wr_ack : out std_logic;
o_dbg_rd_ack : out std_logic;
o_dbg_n_CS : out std_logic_vector(1 downto 0);
o_dbg_n_RAS : out std_logic_vector(1 downto 0);
o_dbg_n_CAS : out std_logic_vector(1 downto 0);
o_dbg_n_WE : out std_logic_vector(1 downto 0);
o_dbg_BA : out std_logic_vector(3 downto 0);
o_dbg_ADDR : out std_logic_vector(25 downto 0);
o_dbg_DATA_out : out std_logic_vector(31 downto 0);
o_dbg_DATA_in : out std_logic_vector(31 downto 0);
i_addr : in std_logic_vector(23 downto 0);
i_din : in std_logic_vector(31 downto 0);
i_dm : in std_logic_vector(3 downto 0);
o_dout : out std_logic_vector(31 downto 0);
o_sdr_state : out std_logic_vector(3 downto 0);
o_sdr_init_done : out std_logic;
o_wr_ack : out std_logic;
o_rd_ack : out std_logic;
o_ref_req : out std_logic;
o_rd_valid : out std_logic;
o_sdr_CKE : out std_logic_vector(1 downto 0);
o_sdr_n_CS : out std_logic_vector(1 downto 0);
o_sdr_n_RAS : out std_logic_vector(1 downto 0);
o_sdr_n_CAS : out std_logic_vector(1 downto 0);
o_sdr_n_WE : out std_logic_vector(1 downto 0);
o_sdr_BA : out std_logic_vector(3 downto 0);
o_sdr_ADDR : out std_logic_vector(25 downto 0);
o_sdr_DATA : out std_logic_vector(31 downto 0);
o_sdr_DATA_oe : out std_logic_vector(31 downto 0);
i_sdr_DATA : in std_logic_vector(31 downto 0);
o_sdr_DQM : out std_logic_vector(3 downto 0);
o_dbg_dly_cnt_b : out std_logic_vector(5 downto 0);
o_dbg_tRCD_done : out std_logic);
END COMPONENT;
---------------------- End COMPONENT Declaration ------------
------------- Begin Cut here for INSTANTIATION Template -----
u_sdram_controller : sdram_controller
PORT MAP (
i_we => i_we,
i_sysclk => i_sysclk,
i_arst => i_arst,
i_sdrclk => i_sdrclk,
i_tACclk => i_tACclk,
i_pll_locked => i_pll_locked,
i_re => i_re,
i_last => i_last,
o_dbg_tRTW_done => o_dbg_tRTW_done,
o_dbg_ref_req => o_dbg_ref_req,
o_dbg_wr_ack => o_dbg_wr_ack,
o_dbg_rd_ack => o_dbg_rd_ack,
o_dbg_n_CS => o_dbg_n_CS,
o_dbg_n_RAS => o_dbg_n_RAS,
o_dbg_n_CAS => o_dbg_n_CAS,
o_dbg_n_WE => o_dbg_n_WE,
o_dbg_BA => o_dbg_BA,
o_dbg_ADDR => o_dbg_ADDR,
o_dbg_DATA_out => o_dbg_DATA_out,
o_dbg_DATA_in => o_dbg_DATA_in,
i_addr => i_addr,
i_din => i_din,
i_dm => i_dm,
o_dout => o_dout,
o_sdr_state => o_sdr_state,
o_sdr_init_done => o_sdr_init_done,
o_wr_ack => o_wr_ack,
o_rd_ack => o_rd_ack,
o_ref_req => o_ref_req,
o_rd_valid => o_rd_valid,
o_sdr_CKE => o_sdr_CKE,
o_sdr_n_CS => o_sdr_n_CS,
o_sdr_n_RAS => o_sdr_n_RAS,
o_sdr_n_CAS => o_sdr_n_CAS,
o_sdr_n_WE => o_sdr_n_WE,
o_sdr_BA => o_sdr_BA,
o_sdr_ADDR => o_sdr_ADDR,
o_sdr_DATA => o_sdr_DATA,
o_sdr_DATA_oe => o_sdr_DATA_oe,
i_sdr_DATA => i_sdr_DATA,
o_sdr_DQM => o_sdr_DQM,
o_dbg_dly_cnt_b => o_dbg_dly_cnt_b,
o_dbg_tRCD_done => o_dbg_tRCD_done);
------------------------ End INSTANTIATION Template ---------

44
hw/efinix_fpga/ip/sdram_controller/settings.json
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@@ -1,44 +0,0 @@
{
"args": [
"-o",
"sdram_controller",
"--base_path",
"/tmp/tmpc6xveluy/ip",
"--vlnv",
{
"vendor": "efinixinc.com",
"library": "memory_controller",
"name": "efx_sdram_controller",
"version": "5.0"
}
],
"conf": {
"fCK_MHz": "200",
"tIORT_u": "2",
"CL": "3",
"DDIO_TYPE": "\"SOFT\"",
"DQ_GROUP": "2",
"ROW_WIDTH": "13",
"COL_WIDTH": "9",
"tPWRUP": "200000",
"tRAS": "44",
"tRAS_MAX": "120000",
"tRC": "66",
"tRCD": "20",
"tREF": "64000000",
"tRFC": "66",
"tRP": "20",
"SDRAM_MODE": "\"Native\"",
"DATA_RATE": "2"
},
"output": {
"external_source_source": [
"/tmp/tmpc6xveluy/ip/sdram_controller/sdram_controller_tmpl.vhd",
"/tmp/tmpc6xveluy/ip/sdram_controller/sdram_controller_define.vh",
"/tmp/tmpc6xveluy/ip/sdram_controller/sdram_controller_tmpl.v",
"/tmp/tmpc6xveluy/ip/sdram_controller/sdram_controller.v"
]
},
"sw_version": "2023.1.150",
"generated_date": "2023-07-16T16:45:19.021917"
}

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hw/efinix_fpga/ip/uart/settings.json
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{
"args": [
"-o",
"uart",
"--base_path",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip",
"--vlnv",
{
"vendor": "efinixinc.com",
"library": "serial_interface",
"name": "efx_uart",
"version": "5.0"
}
],
"conf": {
"BYTE": "1",
"CLOCK_FREQ": "50000000",
"BAUD": "115200",
"ENABLE_PARITY": "1'b0",
"FIX_BAUDRATE": "1'b1",
"PARITY_MODE": "1'b0",
"BOOTUP_CHECK": "1'b0"
},
"output": {
"external_source_source": [
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_tmpl.vhd",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_define.vh",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart_tmpl.v",
"/home/byron/Projects/super6502/hw/efinix_fpga/ip/uart/uart.v"
]
},
"sw_version": "2023.1.150",
"generated_date": "2023-08-06T21:23:16.380430"
}

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hw/efinix_fpga/ip/uart/uart_define.vh
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@@ -1,52 +0,0 @@
// =============================================================================
// Generated by efx_ipmgr
// Version: 2023.1.150
// IP Version: 5.0
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
localparam BYTE = 1;
localparam CLOCK_FREQ = 50000000;
localparam BAUD = 115200;
localparam ENABLE_PARITY = 1'b0;
localparam FIX_BAUDRATE = 1'b1;
localparam PARITY_MODE = 1'b0;
localparam BOOTUP_CHECK = 1'b0;

55
hw/efinix_fpga/ip/uart/uart_tmpl.v
View File

@@ -1,55 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
uart u_uart(
.tx_o ( tx_o ),
.rx_i ( rx_i ),
.tx_busy ( tx_busy ),
.rx_data ( rx_data ),
.rx_data_valid ( rx_data_valid ),
.rx_error ( rx_error ),
.rx_parity_error ( rx_parity_error ),
.rx_busy ( rx_busy ),
.baud_x16_ce ( baud_x16_ce ),
.clk ( clk ),
.reset ( reset ),
.baud_rate ( baud_rate ),
.tx_en ( tx_en ),
.tx_data ( tx_data )
);

76
hw/efinix_fpga/ip/uart/uart_tmpl.vhd
View File

@@ -1,76 +0,0 @@
--------------------------------------------------------------------------------
-- Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
--
-- This document contains proprietary information which is
-- protected by copyright. All rights are reserved. This notice
-- refers to original work by Efinix, Inc. which may be derivitive
-- of other work distributed under license of the authors. In the
-- case of derivative work, nothing in this notice overrides the
-- original author's license agreement. Where applicable, the
-- original license agreement is included in it's original
-- unmodified form immediately below this header.
--
-- WARRANTY DISCLAIMER.
-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
--
-- LIMITATION OF LIABILITY.
-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
-- APPLY TO LICENSEE.
--
--------------------------------------------------------------------------------
------------- Begin Cut here for COMPONENT Declaration ------
COMPONENT uart is
PORT (
tx_o : out std_logic;
rx_i : in std_logic;
tx_busy : out std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_data_valid : out std_logic;
rx_error : out std_logic;
rx_parity_error : out std_logic;
rx_busy : out std_logic;
baud_x16_ce : out std_logic;
clk : in std_logic;
reset : in std_logic;
baud_rate : in std_logic_vector(2 downto 0);
tx_en : in std_logic;
tx_data : in std_logic_vector(7 downto 0));
END COMPONENT;
---------------------- End COMPONENT Declaration ------------
------------- Begin Cut here for INSTANTIATION Template -----
u_uart : uart
PORT MAP (
tx_o => tx_o,
rx_i => rx_i,
tx_busy => tx_busy,
rx_data => rx_data,
rx_data_valid => rx_data_valid,
rx_error => rx_error,
rx_parity_error => rx_parity_error,
rx_busy => rx_busy,
baud_x16_ce => baud_x16_ce,
clk => clk,
reset => reset,
baud_rate => baud_rate,
tx_en => tx_en,
tx_data => tx_data);
------------------------ End INSTANTIATION Template ---------

65
hw/efinix_fpga/simulation/Makefile
View File

@@ -1,65 +0,0 @@
SRCS=$(shell find src/ -type f -name "*.*v")
TBS=$(shell find tbs/ -type f -name "*.*v")
SRCS+=$(shell find ../ip/ -type f -name "*.*v" -not \( -name "*tmpl*" \))
SRCS+=$(shell find ../src/ -type f -name "*.*v")
INC=$(shell find include/ -type f)
TEST_PROGRAM_NAME?=loop_test
TEST_FOLDER?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)
TEST_PROGRAM?=$(REPO_TOP)/sw/test_code/$(TEST_PROGRAM_NAME)/$(TEST_PROGRAM_NAME).hex
STANDALONE_TB= interrupt_controller_tb mapper_tb rtc_tb uart_irq_tb
CODE_TB= interrupt_controller_code_tb mapper_code_tb rtc_code_tb \
devices_setup_code_tb uart_irq_code_tb
#TODO implement something like sources.list
TOP_MODULE=sim_top
TARGET=sim_top
INIT_MEM=init_hex.mem
SD_IMAGE=fs.fat
FLAGS=-DSIM -DRTL_SIM
SD_IMAGE_PATH?=$(REPO_TOP)/sw/script/$(SD_IMAGE)
all: sim
.PHONY: sim
sim: $(TARGET)
vvp -i $(TARGET) -fst
.PHONY: full_sim
full_sim: $(TARGET) $(SD_IMAGE)
vvp -i $(TARGET) -fst
$(STANDALONE_TB): $(SRCS) $(TBS)
iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) tbs/$@.sv
$(CODE_TB): $(SRCS) $(TBS) $(INIT_MEM)
iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(INC) $(SRCS) tbs/$@.sv
$(TARGET): $(INIT_MEM) $(SRCS)
iverilog -g2005-sv $(FLAGS) -s $(TOP_MODULE) -o $(TARGET) $(INC) $(SRCS)
.PHONY: $(INIT_MEM)
$(INIT_MEM):
# Make kernel
$(MAKE) -C $(REPO_TOP)/sw/kernel
$(MAKE) -C $(TEST_FOLDER)
cp $(TEST_PROGRAM) ./init_hex.mem
# The script that makes this file uses relative paths
$(SD_IMAGE):
sh $(REPO_TOP)/sw/script/create_verilog_image.sh
cp $(SD_IMAGE_PATH) $(SD_IMAGE)
.PHONY: clean
clean:
rm -rf $(TARGET)
rm -rf $(INIT_MEM)
rm -rf $(SD_IMAGE)
rm -rf $(STANDALONE_TB)
rm -rf $(CODE_TB)
rm -rf *.vcd

80
hw/efinix_fpga/simulation/include/super6502_sdram_controller_define.vh
View File

@@ -1,80 +0,0 @@
// =============================================================================
// Generated by efx_ipmgr
// Version: 2023.1.150
// IP Version: 5.0
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
localparam fSYS_MHz = 100;
localparam fCK_MHz = 200;
localparam tIORT_u = 2;
localparam CL = 3;
localparam BL = 1;
localparam DDIO_TYPE = "SOFT";
localparam DQ_WIDTH = 8;
localparam DQ_GROUP = 2;
localparam BA_WIDTH = 2;
localparam ROW_WIDTH = 13;
localparam COL_WIDTH = 9;
localparam tPWRUP = 200000;
localparam tRAS = 44;
localparam tRAS_MAX = 120000;
localparam tRC = 66;
localparam tRCD = 20;
localparam tREF = 64000000;
localparam tRFC = 66;
localparam tRP = 20;
localparam tWR = 2;
localparam tMRD = 2;
localparam SDRAM_MODE = "Native";
localparam DATA_RATE = 2;
localparam AXI_AWADDR_WIDTH = 24;
localparam AXI_WDATA_WIDTH = 32;
localparam AXI_ARADDR_WIDTH = 24;
localparam AXI_RDATA_WIDTH = 32;
localparam AXI_AWID_WIDTH = 4;
localparam AXI_AWUSER_WIDTH = 2;
localparam AXI_WUSER_WIDTH = 2;
localparam AXI_BID_WIDTH = 4;
localparam AXI_BUSER_WIDTH = 2;
localparam AXI_ARID_WIDTH = 4;
localparam AXI_ARUSER_WIDTH = 3;
localparam AXI_RUSER_WIDTH = 3;

1145
hw/efinix_fpga/simulation/src/generic_sdr.v
View File

File diff suppressed because it is too large Load Diff

179
hw/efinix_fpga/simulation/src/sim_top.sv
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@@ -1,179 +0,0 @@
`timescale 1ns/1ps
module sim_top();
`include "include/super6502_sdram_controller_define.vh"
logic r_sysclk, r_sdrclk, r_clk_50, r_clk_cpu;
// clk_100
initial begin
r_sysclk <= '1;
forever begin
#5 r_sysclk <= ~r_sysclk;
end
end
// clk_200
initial begin
r_sdrclk <= '1;
forever begin
#2.5 r_sdrclk <= ~r_sdrclk;
end
end
// clk_50
initial begin
r_clk_50 <= '1;
forever begin
#10 r_clk_50 <= ~r_clk_50;
end
end
// clk_cpu
initial begin
r_clk_cpu <= '1;
forever begin
#250 r_clk_cpu <= ~r_clk_cpu;
end
end
// initial begin
// #275000 $finish();
// end
initial begin
$dumpfile("sim_top.vcd");
$dumpvars(0,sim_top);
end
logic button_reset;
initial begin
button_reset <= '0;
repeat(10) @(r_clk_cpu);
button_reset <= '1;
repeat(1500000) @(posedge r_clk_cpu);
$finish();
end
logic w_cpu_reset;
logic [15:0] w_cpu_addr;
logic [7:0] w_cpu_data_from_cpu, w_cpu_data_from_dut;
logic w_cpu_rdy;
logic w_cpu_irqb;
logic w_cpu_we;
logic w_cpu_phi2;
//TODO: this
cpu_65c02 u_cpu(
.phi2(w_cpu_phi2),
.reset(~w_cpu_reset),
.AB(w_cpu_addr),
.RDY(w_cpu_rdy),
.IRQ(~w_cpu_irqb),
.NMI('0),
.DI_s1(w_cpu_data_from_dut),
.DO(w_cpu_data_from_cpu),
.WE(w_cpu_we)
);
logic w_dut_uart_rx, w_dut_uart_tx;
sim_uart u_sim_uart(
.clk_50(r_clk_50),
.reset(~w_cpu_reset),
.rx_i(w_dut_uart_tx),
.tx_o(w_dut_uart_rx)
);
logic w_sd_cs;
logic w_spi_clk;
logic w_spi_mosi;
logic w_spi_miso;
sd_card_emu u_sd_card_emu(
.rst(~w_cpu_reset),
.clk(w_spi_clk),
.cs(w_sd_cs),
.mosi(w_spi_mosi),
.miso(w_spi_miso)
);
super6502 u_dut(
.i_sysclk(r_sysclk),
.i_sdrclk(r_sdrclk),
.i_tACclk(~r_sdrclk),
.clk_50(r_clk_50),
.clk_cpu(r_clk_cpu),
.button_reset(button_reset),
.cpu_resb(w_cpu_reset),
.cpu_addr(w_cpu_addr),
.cpu_data_out(w_cpu_data_from_dut),
.cpu_data_in(w_cpu_data_from_cpu),
.cpu_rwb(~w_cpu_we),
.cpu_rdy(w_cpu_rdy),
.cpu_phi2(w_cpu_phi2),
.cpu_irqb(w_cpu_irqb),
.uart_rx(w_dut_uart_rx),
.uart_tx(w_dut_uart_tx),
.sd_cs(w_sd_cs),
.spi_clk(w_spi_clk),
.spi_mosi(w_spi_mosi),
.spi_miso(w_spi_miso),
.o_sdr_CKE(w_sdr_CKE),
.o_sdr_n_CS(w_sdr_n_CS),
.o_sdr_n_WE(w_sdr_n_WE),
.o_sdr_n_RAS(w_sdr_n_RAS),
.o_sdr_n_CAS(w_sdr_n_CAS),
.o_sdr_BA(w_sdr_BA),
.o_sdr_ADDR(w_sdr_ADDR),
.i_sdr_DATA(w_sdr_DQ),
.o_sdr_DATA(w_sdr_DATA),
.o_sdr_DATA_oe(w_sdr_DATA_oe),
.o_sdr_DQM(w_sdr_DQM)
);
wire w_sdr_CKE;
wire w_sdr_n_CS;
wire w_sdr_n_WE;
wire w_sdr_n_RAS;
wire w_sdr_n_CAS;
wire [BA_WIDTH -1:0]w_sdr_BA;
wire [ROW_WIDTH -1:0]w_sdr_ADDR;
wire [DQ_GROUP *DQ_WIDTH -1:0]w_sdr_DATA;
wire [DQ_GROUP *DQ_WIDTH -1:0]w_sdr_DATA_oe;
wire [DQ_GROUP -1:0]w_sdr_DQM;
wire [DQ_GROUP *DQ_WIDTH -1:0]w_sdr_DQ;
genvar i, j;
generate
for (i=0; i<DQ_GROUP*DQ_WIDTH; i=i+1)
begin: DQ_map
assign w_sdr_DQ[i] = (w_sdr_DATA_oe[i])?
w_sdr_DATA[i]:1'bz;
end
for (j=0; j<DQ_GROUP; j=j+1)
begin : mem_inst
generic_sdr inst_sdr
(
.Dq(w_sdr_DQ[((j+1)*(DQ_WIDTH))-1:((j)*DQ_WIDTH)]),
.Addr(w_sdr_ADDR[ROW_WIDTH-1:0]),
.Ba(w_sdr_BA[BA_WIDTH-1:0]),
.Clk(~r_sdrclk),
.Cke(w_sdr_CKE),
.Cs_n(w_sdr_n_CS),
.Ras_n(w_sdr_n_RAS),
.Cas_n(w_sdr_n_CAS),
.We_n(w_sdr_n_WE),
.Dqm(w_sdr_DQM[j])
);
end
endgenerate
endmodule

43
hw/efinix_fpga/simulation/src/sim_uart/sim_uart.sv
View File

@@ -1,43 +0,0 @@
module sim_uart(
input clk,
input clk_50,
input reset,
input [7:0] i_data,
input rx_i,
output tx_o
);
logic tx_busy, rx_busy;
logic rx_data_valid, rx_error, rx_parity_error;
logic baud_x16_ce;
logic tx_en;
logic [7:0] tx_data, rx_data;
uart u_uart(
.tx_o ( tx_o ),
.rx_i ( rx_i ),
.tx_busy ( tx_busy ),
.rx_data ( rx_data ),
.rx_data_valid ( rx_data_valid ),
.rx_error ( rx_error ),
.rx_parity_error ( rx_parity_error ),
.rx_busy ( rx_busy ),
.baud_x16_ce ( baud_x16_ce ),
.clk ( clk_50 ),
.reset ( reset ),
.tx_data ( tx_data ),
.baud_rate ( baud_rate ),
.tx_en ( tx_en )
);
always @(posedge baud_x16_ce) begin
if (rx_data_valid)
$display("UART: %c", rx_data);
end
endmodule

1
hw/efinix_fpga/simulation/src/verilog-6502

Submodule hw/efinix_fpga/simulation/src/verilog-6502 deleted from aaf4c084ef

1
hw/efinix_fpga/simulation/src/verilog-sd-emulator

Submodule hw/efinix_fpga/simulation/src/verilog-sd-emulator deleted from 72a7868fa9

27
hw/efinix_fpga/simulation/tbs/devices_setup_code_tb.sv
View File

@@ -1,27 +0,0 @@
`timescale 1ns/1ps
module devices_setup_code_tb();
sim_top u_sim_top();
always begin
if (
u_sim_top.w_cpu_addr == 16'h0 &&
u_sim_top.w_cpu_we == '1
) begin
if (u_sim_top.w_cpu_data_from_cpu == 8'h6d) begin
$display("Good finish!");
$finish();
end else begin
$display("Bad finish!");
$finish_and_return(-1);
end
end
# 1;
end
always @(u_sim_top.u_dut.u_rtc.r_output) begin
$display("counter: %d", u_sim_top.u_dut.u_rtc.r_output);
end
endmodule

39
hw/efinix_fpga/simulation/tbs/interrupt_controller_code_tb.sv
View File

@@ -1,39 +0,0 @@
`timescale 1ns/1ps
module interrupt_controller_code_tb();
sim_top u_sim_top();
always begin
if (
u_sim_top.w_cpu_addr == 16'h0 &&
u_sim_top.w_cpu_we == '1
) begin
if (u_sim_top.w_cpu_data_from_cpu == 8'h6d) begin
$display("Good finish!");
$finish();
end else begin
$display("Bad finish!");
$finish_and_return(-1);
end
end
# 1;
end
initial begin
// u_sim_top.u_dut.w_int_in = 0;
repeat (2400) @(posedge u_sim_top.r_clk_cpu);
for (int i = 0; i < 128; i++) begin
repeat (100) @(posedge u_sim_top.r_clk_cpu);
force u_sim_top.u_dut.u_interrupt_controller.int_in = 1 << i;
$display("Activiating interrupt %d", i);
end
end
initial begin
repeat (40000) @(posedge u_sim_top.r_clk_cpu);
$display("Timed out");
$finish_and_return(-1);
end
endmodule

209
hw/efinix_fpga/simulation/tbs/interrupt_controller_tb.sv
View File

@@ -1,209 +0,0 @@
`timescale 1ns/1ps
module interrupt_controller_tb();
logic r_clk_cpu;
localparam BITS_128 = 128'hffffffffffffffffffffffffffffffff;
// clk_cpu
initial begin
r_clk_cpu <= '1;
forever begin
#125 r_clk_cpu <= ~r_clk_cpu;
end
end
logic reset;
logic addr;
logic [7:0] i_data;
logic [7:0] o_data;
logic cs;
logic rwb;
logic [127:0] int_in;
logic int_out;
interrupt_controller #(
.N_INTERRUPTS(128)
) u_interrupt_controller (
.clk(r_clk_cpu),
.reset(reset),
.i_data(i_data),
.o_data(o_data),
.addr(addr),
.cs(cs),
.rwb(rwb),
.int_in(int_in),
.int_out(int_out)
);
/* Test Level triggered IRQ by triggering IRQ0
* and then clearing it,
*/
task test_edge_irq();
$display("Testing Edge IRQ");
do_reset();
set_enable(128'hff);
set_edge_type(128'h0);
set_interrupts(1);
assert (int_out == 1) else begin
errors = errors + 1;
$error("Interrupt should be high!");
end
send_eoi();
assert (int_out == 0) else begin
errors = errors + 1;
$error("Interrupt should be low!");
end
set_interrupts(0);
assert (int_out == 0) else begin
errors = errors + 1;
$error("Interrupt should be low!");
end
endtask
task test_level_irq();
$display("Testing level IRQ");
do_reset();
set_enable(128'hff);
set_edge_type(128'hff);
set_interrupts(1);
assert (int_out == 1) else begin
errors = errors + 1;
$error("Interrupt should be high!");
end
send_eoi();
assert (int_out == 1) else begin
errors = errors + 1;
$error("Interrupt should be high!");
end
set_interrupts(0);
send_eoi();
assert (int_out == 0) else begin
errors = errors + 1;
$error("Interrupt should be low!");
end
endtask
task test_irq_val();
int irq_val = -1;
$display("Testing IRQ val output");
do_reset();
set_enable('1);
set_edge_type('1);
for (int i = 127; i >= 0; i--) begin
set_interrupts(BITS_128 << i);
read_irqval(irq_val);
assert(i == irq_val) else begin
errors = errors + 1;
$display("Expected %d got %d", i, irq_val);
end
end
for (int i = 0; i < 128; i++) begin
set_interrupts(BITS_128 >> i);
read_irqval(irq_val);
assert(int_out == 1) else begin
errors = errors + 1;
$display("int_out should be asserted!");
end
assert(0 == irq_val) else begin
errors = errors + 1;
$display("Expected %d got %d", i, irq_val);
end
end
endtask
int errors;
initial begin
errors = 0;
test_edge_irq();
test_level_irq();
test_irq_val();
if (errors > 0)
$finish_and_return(-1);
else
$finish();
end
initial
begin
$dumpfile("interrupt_controller_tb.vcd");
$dumpvars(0,interrupt_controller_tb);
end
/* These should be shared */
task write_reg(input logic [4:0] _addr, input logic [7:0] _data);
@(negedge r_clk_cpu);
cs <= '1;
addr <= _addr;
rwb <= '0;
i_data <= '1;
@(posedge r_clk_cpu);
i_data <= _data;
@(negedge r_clk_cpu);
cs <= '0;
rwb <= '1;
@(posedge r_clk_cpu);
endtask
task read_reg(input logic [2:0] _addr, output logic [7:0] _data);
@(negedge r_clk_cpu);
cs <= '1;
addr <= _addr;
rwb <= '1;
i_data <= '1;
@(posedge r_clk_cpu);
_data <= o_data;
@(negedge r_clk_cpu);
cs <= '0;
rwb <= '1;
@(posedge r_clk_cpu);
endtask
task do_reset();
repeat (5) @(posedge r_clk_cpu);
reset = 1;
cs = 0;
rwb = 1;
addr = '0;
i_data = '0;
int_in = '0;
repeat (5) @(posedge r_clk_cpu);
reset = 0;
repeat (5) @(posedge r_clk_cpu);
endtask
task set_enable(input logic [127:0] en);
for (int i = 0; i < 16; i++) begin
write_reg(0, 8'h20 | i);
write_reg(1, en[8*i +: 8]);
end
endtask
task set_edge_type(input logic [127:0] edge_type);
for (int i = 0; i < 16; i++) begin
write_reg(0, 8'h40 | i);
write_reg(1, edge_type[8*i +: 8]);
end
endtask
task set_interrupts(logic [127:0] ints);
int_in = ints;
@(posedge r_clk_cpu);
endtask
task send_eoi();
write_reg(0, 8'hff);
write_reg(1, 8'h01);
endtask
task read_irqval(output logic [7:0] _irq_val);
write_reg(0, 8'h00);
read_reg(1, _irq_val);
endtask
endmodule

23
hw/efinix_fpga/simulation/tbs/mapper_code_tb.sv
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@@ -1,23 +0,0 @@
`timescale 1ns/1ps
module mapper_code_tb();
sim_top u_sim_top();
always begin
if (
u_sim_top.w_cpu_addr == 16'h0 &&
u_sim_top.w_cpu_we == '1
) begin
if (u_sim_top.w_cpu_data_from_cpu == 8'h6d) begin
$display("Good finish!");
$finish();
end else begin
$display("Bad finish!");
$finish_and_return(-1);
end
end
# 1;
end
endmodule

125
hw/efinix_fpga/simulation/tbs/mapper_tb.sv
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@@ -1,125 +0,0 @@
`timescale 1ns/1ps
module mapper_tb();
logic r_clk_cpu;
// clk_cpu
initial begin
r_clk_cpu <= '1;
forever begin
#125 r_clk_cpu <= ~r_clk_cpu;
end
end
logic reset;
logic [15:0] addr;
logic [24:0] map_addr;
logic [7:0] i_data;
logic [7:0] o_data;
logic cs;
logic rwb;
mapper u_mapper(
.i_reset(reset),
.i_clk(r_clk_cpu),
.i_cs(cs),
.i_we(~rwb),
.i_data(i_data),
.o_data(o_data),
.i_cpu_addr(addr),
.o_mapped_addr(map_addr)
);
/* These could be made better probably */
task write_reg(input logic [4:0] _addr, input logic [7:0] _data);
@(negedge r_clk_cpu);
cs <= '1;
addr <= _addr;
rwb <= '0;
i_data <= '1;
@(posedge r_clk_cpu);
i_data <= _data;
@(negedge r_clk_cpu);
cs <= '0;
rwb <= '1;
endtask
task read_reg(input logic [2:0] _addr, output logic [7:0] _data);
@(negedge r_clk_cpu);
cs <= '1;
addr <= _addr;
rwb <= '1;
i_data <= '1;
@(posedge r_clk_cpu);
_data <= o_data;
@(negedge r_clk_cpu);
cs <= '0;
rwb <= '1;
endtask
int errors;
int rnd_values [16];
int rnd_addr;
initial begin
for (int i = 0; i < 16; i++) begin
rnd_values[i] = $urandom();
end
errors = 0;
repeat (5) @(posedge r_clk_cpu);
reset = 1;
cs = 0;
rwb = 1;
addr = '0;
i_data = '0;
repeat (5) @(posedge r_clk_cpu);
reset = 0;
repeat (5) @(posedge r_clk_cpu);
for (int i = 0; i < 16; i++) begin
write_reg(2*i, rnd_values[i][7:0]);
write_reg(2*i + 1, rnd_values[i][15:8]);
end
repeat (5) @(posedge r_clk_cpu);
for (int i = 0; i < 16; i++) begin
assert (u_mapper.mm[i] == rnd_values[i][15:0]) else begin
$error("mm[%d] expected 0x%x got 0x%x", i, rnd_values[i][15:0], u_mapper.mm[i]);
errors += 1;
end
end
for (int i = 0; i < 16; i++) begin
rnd_addr = $urandom();
addr = i << 12 | rnd_addr[11:0];
#1 // Neccesary for this assertion to work
assert (map_addr == {rnd_values[i][12:0], rnd_addr[11:0]}) else begin
$error("Expected %x got %x", {rnd_values[i][12:0], rnd_addr[11:0]}, map_addr);
end
@(posedge r_clk_cpu);
end
if (errors != 0) begin
$finish_and_return(-1);
end else begin
$finish();
end
end
initial
begin
$dumpfile("mapper_tb.vcd");
$dumpvars(0,mapper_tb);
for (int i = 0; i < 16; i++) $dumpvars(0, u_mapper.mm[i]);
end
endmodule

49
hw/efinix_fpga/simulation/tbs/rtc_code_tb.sv
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@@ -1,49 +0,0 @@
`timescale 1ns/1ps
module rtc_code_tb();
sim_top u_sim_top();
always begin
if (
u_sim_top.w_cpu_addr == 16'h0 &&
u_sim_top.w_cpu_we == '1
) begin
if (u_sim_top.w_cpu_data_from_cpu == 8'h6d) begin
$display("Good finish!");
$finish();
end else begin
$display("Bad finish!");
$finish_and_return(-1);
end
end
# 1;
end
localparam increment = 3;
logic [7:0] prev;
initial prev = '0;
always @(u_sim_top.w_cpu_addr) begin
if (
u_sim_top.w_cpu_addr == 16'h1 &&
u_sim_top.w_cpu_we == '1
) begin
if (u_sim_top.w_cpu_data_from_cpu <= prev) begin
$display("Value didn't increment!");
$display("Bad finish!");
$finish_and_return(-1);
end
prev = u_sim_top.w_cpu_data_from_cpu;
$display("print1: %x", u_sim_top.w_cpu_data_from_cpu);
end
end
initial begin
repeat (5000) @(posedge u_sim_top.r_clk_cpu);
$display("Timed out");
$finish_and_return(-1);
end
endmodule

117
hw/efinix_fpga/simulation/tbs/rtc_tb.sv
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@@ -1,117 +0,0 @@
`timescale 1ns/1ps
module rtc_tb();
logic r_clk_cpu;
initial begin
r_clk_cpu <= '1;
forever begin
#125 r_clk_cpu <= ~r_clk_cpu;
end
end
logic reset, rwb, cs, addr, irq;
logic [7:0] i_data, o_data;
rtc u_rtc(
.clk(r_clk_cpu),
.reset(reset),
.rwb(rwb),
.cs(cs),
.addr(addr),
.i_data(i_data),
.o_data(o_data),
.irq(irq)
);
initial begin
do_reset();
set_increment(1);
set_threshold(7);
set_irq_threshold(2);
enable_rtc(3);
repeat (20) @(posedge r_clk_cpu);
$finish();
end
initial begin
$dumpfile("rtc_tb.vcd");
$dumpvars(0,rtc_tb);
end
task do_reset();
repeat (5) @(posedge r_clk_cpu);
reset = 1;
cs = 0;
rwb = 1;
addr = '0;
i_data = '0;
repeat (5) @(posedge r_clk_cpu);
reset = 0;
repeat (5) @(posedge r_clk_cpu);
endtask
/* These should be shared */
task write_reg(input logic [4:0] _addr, input logic [7:0] _data);
@(negedge r_clk_cpu);
cs <= '1;
addr <= _addr;
rwb <= '0;
i_data <= '1;
@(posedge r_clk_cpu);
i_data <= _data;
@(negedge r_clk_cpu);
cs <= '0;
rwb <= '1;
@(posedge r_clk_cpu);
endtask
task read_reg(input logic [2:0] _addr, output logic [7:0] _data);
@(negedge r_clk_cpu);
cs <= '1;
addr <= _addr;
rwb <= '1;
i_data <= '1;
@(posedge r_clk_cpu);
_data <= o_data;
@(negedge r_clk_cpu);
cs <= '0;
rwb <= '1;
@(posedge r_clk_cpu);
endtask
task set_increment(input logic [31:0] _increment);
for (int i = 0; i < 4; i++) begin
write_reg(0, 8'h10 | i);
write_reg(1, _increment[8*i +: 8]);
end
endtask
task set_threshold(input logic [31:0] _threshold);
for (int i = 0; i < 4; i++) begin
write_reg(0, 8'h00 | i);
write_reg(1, _threshold[8*i +: 8]);
end
endtask
task set_irq_threshold(input logic [31:0] _increment);
for (int i = 0; i < 4; i++) begin
write_reg(0, 8'h20 | i);
write_reg(1, _increment[8*i +: 8]);
end
endtask
task enable_rtc(input logic [7:0] _ctrl);
write_reg(0, 8'h30);
write_reg(1, _ctrl);
endtask
task read_output(output logic [31:0] _output);
for (int i = 0; i < 4; i++) begin
write_reg(0, 8'h30 | i);
read_reg(1, _output[8*i +: 8]);
end
endtask
endmodule

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