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Start over pretty much.

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Byron Lathi
2022-12-19 23:12:22 -05:00
parent 3a70c4f523
commit 09e31fe7ab
30 changed files with 577 additions and 7186 deletions
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28
hw/efinix_fpga/super6502.xml
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@@ -1,35 +1,22 @@
<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="super6502" description="" last_change_date="Wed August 17 2022 12:17:48" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2021.2.323.4.6" last_run_state="fail" last_run_tool="efx_map" last_run_flow="syn" config_result_in_sync="true" design_ood="" place_ood="" route_ood="" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:project name="super6502" description="" last_change_date="Tue November 1 2022 18:28:14" location="/home/byron/Projects/super6502/hw/efinix_fpga" sw_version="2021.2.323.4.6" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Trion"/>
<efx:device name="T20F256"/>
<efx:timing_model name="C3"/>
<efx:timing_model name="C4"/>
</efx:device_info>
<efx:design_info def_veri_version="sv_09" def_vhdl_version="vhdl_2008">
<efx:top_module name="super6502"/>
<efx:top_module name=""/>
<efx:design_file name="super6502.sv" version="default" library="default"/>
<efx:design_file name="crc7.sv" version="default" library="default"/>
<efx:design_file name="memory_mapper.sv" version="default" library="default"/>
<efx:design_file name="uart.sv" version="default" library="default"/>
<efx:design_file name="HexDriver.sv" version="default" library="default"/>
<efx:design_file name="addr_decode.sv" version="default" library="default"/>
<efx:design_file name="board_io.sv" version="default" library="default"/>
<efx:design_file name="SevenSeg.sv" version="default" library="default"/>
<efx:design_file name="sd_controller.sv" version="default" library="default"/>
<efx:design_file name="sdram_adapter.sv" version="default" library="default"/>
<efx:top_vhdl_arch name=""/>
</efx:design_info>
<efx:constraint_info>
<efx:sdc_file name=""/>
<efx:sdc_file name="super6502.pt.sdc"/>
<efx:inter_file name=""/>
</efx:constraint_info>
<efx:sim_info/>
<efx:misc_info/>
<efx:ip_info>
<efx:ip instance_name="sdram" path="ip/sdram/settings.json">
<efx:ip_src_file name="sdram.v"/>
</efx:ip>
</efx:ip_info>
<efx:ip_info/>
<efx:synthesis tool_name="efx_map">
<efx:param name="work_dir" value="work_syn" value_type="e_string"/>
<efx:param name="write_efx_verilog" value="on" value_type="e_bool"/>
@@ -47,7 +34,6 @@
<efx:param name="optimize-adder-tree" value="0" value_type="e_option"/>
<efx:param name="mult_input_regs_packing" value="1" value_type="e_option"/>
<efx:param name="mult_output_regs_packing" value="1" value_type="e_option"/>
<efx:param name="include" value="ip/sdram" value_type="e_string"/>
</efx:synthesis>
<efx:place_and_route tool_name="efx_pnr">
<efx:param name="work_dir" value="work_pnr" value_type="e_string"/>
@@ -77,7 +63,7 @@
</efx:bitstream_generation>
<efx:debugger>
<efx:param name="work_dir" value="work_dbg" value_type="e_string"/>
<efx:param name="auto_instantiation" value="off" value_type="e_bool"/>
<efx:param name="profile" value="NONE" value_type="e_string"/>
<efx:param name="auto_instantiation" value="on" value_type="e_bool"/>
<efx:param name="profile" value="debug_profile.wizard.json" value_type="e_string"/>
</efx:debugger>
</efx:project>