Delete everything
This commit is contained in:
Byron Lathi
@@ -1,293 +0,0 @@
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||||
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Binary file not shown.
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Before Width: | Height: | Size: 122 KiB |
@@ -1,70 +0,0 @@
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# Memory Mapper
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## Overview
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The memory mapper gives expands the CPU's address space from 16 bits to 25.
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It can be expanded to be 28 bits, but only 25 are needed to access all of
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sdram.
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Its architecture is show below:
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There are 32 16 bit registers: One for each 4k page in the virtual address
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space. The memory mapper is always enabled, but at reset it is identity
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mapped, i.e. register _n_ will be reset to value _n_.
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## Interface
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The Memory mapper is composed of 32 identical 16 bit mapping registers
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The chip select should be calculated based on the virtual address. If not,
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it will be possible for the CPU to map away access to the mapper, at which
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point it is impossible to change the mappings without a reset.
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## Registers
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### Register Map
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| Address | Read | Write |
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|--------- |-------------- |-------------- |
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| 00 | MM0 Low | MM0 Low |
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| 01 | MM0 High | MM0 High |
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| 02 | MM1 Low | MM1 Low |
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| 03 | MM1 High | MM1 High |
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| 04 | MM2 Low | MM2 Low |
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| 05 | MM2 High | MM2 High |
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| 06 | MM3 Low | MM3 Low |
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| 07 | MM3 High | MM3 High |
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| 08 | MM4 Low | MM4 Low |
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| 09 | MM4 High | MM4 High |
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| 0A | MM5 Low | MM5 Low |
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| 0B | MM5 High | MM5 High |
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| 0C | MM6 Low | MM6 Low |
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| 0D | MM6 High | MM6 High |
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| 0E | MM7 Low | MM7 Low |
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| 0F | MM7 High | MM7 High |
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| 10 | MM8 Low | MM8 Low |
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| 11 | MM8 High | MM8 High |
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| 12 | MM9 Low | MM9 Low |
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| 13 | MM9 High | MM9 High |
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| 14 | MM10 Low | MM10 Low |
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| 15 | MM10 High | MM10 High |
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| 16 | MM11 Low | MM11 Low |
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| 17 | MM11 High | MM11 High |
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| 18 | MM12 Low | MM12 Low |
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| 19 | MM12 High | MM12 High |
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| 1A | MM13 Low | MM13 Low |
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| 1B | MM13 High | MM13 High |
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| 1C | MM14 Low | MM14 Low |
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| 1D | MM14 High | MM14 High |
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| 1E | MM15 Low | MM15 Low |
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| 1F | MM15 High | MM15 High |
|
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### MMn Low
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|
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Low memory map data. Becomes bits [19:12] of physical address.
|
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|
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### MMn High
|
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|
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High memory map data. Becomes bits [27:20] of physical address.
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@@ -1,405 +0,0 @@
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Binary file not shown.
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Before Width: | Height: | Size: 140 KiB |
@@ -1,60 +0,0 @@
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# PIC
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||||
|
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## Overview
|
||||
|
||||
The PIC (Programmable Interrupt Controller) supports 256 edge or level
|
||||
triggered interrupts.
|
||||
|
||||
Interrupts can only be rising edge or positive level trigger. Negative edge or
|
||||
low level trigger can be accomplished by inverting the input to this module.
|
||||
|
||||
When an interrupt is triggered, it remains triggered until cleared with an
|
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`EOI`. Currently, only the highest priority interrupt can be cleared. This
|
||||
is bad design and will be fixed soon(tm).
|
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|
||||
|
||||
|
||||
## Interface
|
||||
|
||||
The PIC is controlled through two 8-bit registers, `CMD` and `DAT`.
|
||||
The upepr 3 bits of `CMD` control which register is accessed, and the lower 5
|
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bits control the byte select.
|
||||
|
||||
`EOI` is a special case: when `CMD` is 0xFF, the highest priority interrupt is
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||||
cleared.
|
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|
||||
### CMD
|
||||
| [7:5] | [4:0] |
|
||||
|------------------ |------------- |
|
||||
| Register Address | Byte Select |
|
||||
|
||||
### DAT
|
||||
| [7:0] |
|
||||
|----------------------- |
|
||||
| Data[8*Byte_sel +: 8] |
|
||||
|
||||
## Registers
|
||||
|
||||
### Register Map
|
||||
|
||||
| Address | Read | Write |
|
||||
|--------- |------------ |-------- |
|
||||
| 0 | IRQ Number | ~ |
|
||||
| 1 | Enable | Enable |
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| 2 | Type | Type |
|
||||
|
||||
### IRQ Number
|
||||
|
||||
8 bit register outputs the highest priority interrupt currently active. When
|
||||
no interrupt is active, it will output 255.
|
||||
|
||||
### Enable
|
||||
|
||||
256 bit enable register. When bit _n_ is set to 1, the corresponding interrupt
|
||||
_n_.
|
||||
|
||||
### Type
|
||||
|
||||
256 bit type register. When bit _n_ is set to 0, the corresponding interrupt
|
||||
_n_ will be edge triggered. If the bit is set to 1, the interrupt will be level
|
||||
triggered.
|
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@@ -1,159 +0,0 @@
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Before Width: | Height: | Size: 46 KiB |
@@ -1,82 +0,0 @@
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# RTC
|
||||
|
||||
## Overview
|
||||
|
||||
The RTC is capable of keeping track of elapsed time as well as generating
|
||||
periodic interrupts. Its input frequency is (currently) the same as the CPU
|
||||
frequency. The architecture is shown below:
|
||||
|
||||
|
||||
|
||||
The `counter` register is a 32 bit register which increments by `increment`
|
||||
every clock tick. When this value reaches `threshold`, both `output` and
|
||||
`irq_counter` are incremented by 1. When `irq_counter` reaches `irq_threshold`,
|
||||
an interrupt is generated.
|
||||
|
||||
The interrupt frequency can be calculated with the following equations:
|
||||
|
||||
$$ F_{out}=\frac{F_{in}\cdot{increment}}{threshold} $$
|
||||
$$ F_{irq}=\frac{F_{out}}{irq\_threshold} $$
|
||||
|
||||
Where $ F_{out} $ is the frequency at which the output changes and $ F_{irq} $
|
||||
is the frequency at which interrupts occur.
|
||||
|
||||
## Interface
|
||||
|
||||
The RTC is controlled through two 8-bit registers, `CMD` and `DAT`.
|
||||
The upepr 4 bits of `CMD` control which register is accessed, and the lower 4
|
||||
bits control the byte select. The RTC uses 32 bit registers, so only values of
|
||||
0-3 are supported.
|
||||
|
||||
### CMD
|
||||
| [7:4] | [3:2 | [1:0] |
|
||||
|------------------ |---------- |------------- |
|
||||
| Register Address | Reserved | Byte Select |
|
||||
|
||||
### DAT
|
||||
| [7:0] |
|
||||
|----------------------- |
|
||||
| Data[8*Byte_sel +: 8] |
|
||||
|
||||
## Registers
|
||||
|
||||
### Register Map
|
||||
|
||||
| Address | Read | Write |
|
||||
|--------- |--------------- |--------------- |
|
||||
| 0 | Threshold | Threshold |
|
||||
| 1 | Increment | Increment |
|
||||
| 2 | IRQ Threshold | IRQ Threshold |
|
||||
| 3 | Output | Control |
|
||||
|
||||
### Threshold
|
||||
|
||||
32 bit threshold register. When `counter` reaches this value, `output` and
|
||||
`irq_counter` are incremented by 1, and `counter` is reset back to 0.
|
||||
|
||||
### Increment
|
||||
|
||||
32 bit increment register. Every clock cycle, `counter` is incremented by
|
||||
`increment`
|
||||
|
||||
### IRQ Threshold
|
||||
|
||||
32 bit IRQ threshold register. When `irq_counter` reaches this value, and IRQ
|
||||
is generated and `irq_counter` is reset back to 0.
|
||||
|
||||
### Output
|
||||
|
||||
32 bit output register. This value ticks up.
|
||||
|
||||
### Control
|
||||
|
||||
| [7:2] | [1] | [0] |
|
||||
|---------- |------------ |-------- |
|
||||
| Reserved | IRQ Enable | Enable |
|
||||
|
||||
8 bit Control register. Regardless of Byte Select, any write to address 3 will
|
||||
write to this register. `IRQ Enable` controls interrupt generation. `Enable` is
|
||||
a global enable. When 0, all counter registers are set to 0.
|
||||
|
||||
|
||||
|
||||
107
doc/top.drawio
107
doc/top.drawio
@@ -1,107 +0,0 @@
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Reference in New Issue
Block a user