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Add sdram, don't think it works though

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Byron Lathi
2024-03-03 20:43:37 -08:00
parent 78dfb01bd7
commit 10a72d8e1f
17 changed files with 6256 additions and 31 deletions
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hw/super6502_fpga/ip/sdram_controller/ipm/component.pickle Normal file
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hw/super6502_fpga/ip/sdram_controller/ipm/graph.pickle Normal file
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hw/super6502_fpga/ip/sdram_controller/sdram_controller.v Normal file
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hw/super6502_fpga/ip/sdram_controller/sdram_controller_define.vh Normal file
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// =============================================================================
// Generated by efx_ipmgr
// Version: 2023.1.150
// IP Version: 5.0
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
localparam fSYS_MHz = 100;
localparam fCK_MHz = 200;
localparam tIORT_u = 2;
localparam CL = 3;
localparam BL = 1;
localparam DDIO_TYPE = "SOFT";
localparam DQ_WIDTH = 8;
localparam DQ_GROUP = 2;
localparam BA_WIDTH = 2;
localparam ROW_WIDTH = 13;
localparam COL_WIDTH = 9;
localparam tPWRUP = 200000;
localparam tRAS = 44;
localparam tRAS_MAX = 120000;
localparam tRC = 66;
localparam tRCD = 20;
localparam tREF = 64000000;
localparam tRFC = 66;
localparam tRP = 20;
localparam tWR = 2;
localparam tMRD = 2;
localparam SDRAM_MODE = "AXI4";
localparam DATA_RATE = 2;
localparam AXI_AWADDR_WIDTH = 24;
localparam AXI_WDATA_WIDTH = 32;
localparam AXI_ARADDR_WIDTH = 24;
localparam AXI_RDATA_WIDTH = 32;
localparam AXI_AWID_WIDTH = 4;
localparam AXI_AWUSER_WIDTH = 2;
localparam AXI_WUSER_WIDTH = 2;
localparam AXI_BID_WIDTH = 4;
localparam AXI_BUSER_WIDTH = 2;
localparam AXI_ARID_WIDTH = 4;
localparam AXI_ARUSER_WIDTH = 3;
localparam AXI_RUSER_WIDTH = 3;

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hw/super6502_fpga/ip/sdram_controller/sdram_controller_tmpl.v Normal file
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////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
sdram_controller u_sdram_controller(
.i_aresetn ( i_aresetn ),
.i_AXI4_AWADDR ( i_AXI4_AWADDR ),
.i_sysclk ( i_sysclk ),
.i_sdrclk ( i_sdrclk ),
.i_tACclk ( i_tACclk ),
.i_pll_locked ( i_pll_locked ),
.o_dbg_ref_req ( o_dbg_ref_req ),
.o_dbg_wr_ack ( o_dbg_wr_ack ),
.o_dbg_rd_ack ( o_dbg_rd_ack ),
.o_dbg_n_CS ( o_dbg_n_CS ),
.o_dbg_n_RAS ( o_dbg_n_RAS ),
.o_dbg_n_CAS ( o_dbg_n_CAS ),
.o_dbg_n_WE ( o_dbg_n_WE ),
.o_dbg_BA ( o_dbg_BA ),
.o_dbg_ADDR ( o_dbg_ADDR ),
.o_dbg_DATA_out ( o_dbg_DATA_out ),
.o_dbg_DATA_in ( o_dbg_DATA_in ),
.o_pll_reset ( o_pll_reset ),
.o_AXI4_AWREADY ( o_AXI4_AWREADY ),
.i_AXI4_AWVALID ( i_AXI4_AWVALID ),
.o_AXI4_WREADY ( o_AXI4_WREADY ),
.i_AXI4_WDATA ( i_AXI4_WDATA ),
.i_AXI4_WSTRB ( i_AXI4_WSTRB ),
.i_AXI4_WLAST ( i_AXI4_WLAST ),
.i_AXI4_WVALID ( i_AXI4_WVALID ),
.o_AXI4_BVALID ( o_AXI4_BVALID ),
.i_AXI4_BREADY ( i_AXI4_BREADY ),
.o_AXI4_ARREADY ( o_AXI4_ARREADY ),
.i_AXI4_ARADDR ( i_AXI4_ARADDR ),
.i_AXI4_RREADY ( i_AXI4_RREADY ),
.o_AXI4_RDATA ( o_AXI4_RDATA ),
.o_AXI4_RLAST ( o_AXI4_RLAST ),
.o_AXI4_RVALID ( o_AXI4_RVALID ),
.i_AXI4_AWID ( i_AXI4_AWID ),
.i_AXI4_AWSIZE ( i_AXI4_AWSIZE ),
.i_AXI4_ARVALID ( i_AXI4_ARVALID ),
.i_AXI4_ARID ( i_AXI4_ARID ),
.i_AXI4_ARLEN ( i_AXI4_ARLEN ),
.i_AXI4_ARSIZE ( i_AXI4_ARSIZE ),
.i_AXI4_ARBURST ( i_AXI4_ARBURST ),
.i_AXI4_AWLEN ( i_AXI4_AWLEN ),
.o_AXI4_RID ( o_AXI4_RID ),
.o_dbg_we ( o_dbg_we ),
.o_dbg_last ( o_dbg_last ),
.o_dbg_addr ( o_dbg_addr ),
.o_dbg_din ( o_dbg_din ),
.o_axi4_wrstate ( o_axi4_wrstate ),
.o_fifo_wr ( o_fifo_wr ),
.o_fifo_full ( o_fifo_full ),
.o_fifo_empty ( o_fifo_empty ),
.o_dbg_fifo_waddr ( o_dbg_fifo_waddr ),
.o_dbg_fifo_re ( o_dbg_fifo_re ),
.o_dbg_fifo_raddr ( o_dbg_fifo_raddr ),
.o_dbg_fifo_we ( o_dbg_fifo_we ),
.o_dbg_axi4_wlast ( o_dbg_axi4_wlast ),
.o_shift_cnt ( o_shift_cnt ),
.o_re_lock ( o_re_lock ),
.o_axi4_rastate ( o_axi4_rastate ),
.o_axi4_nwr ( o_axi4_nwr ),
.o_axi4_arlen ( o_axi4_arlen ),
.o_axi4_rdstate ( o_axi4_rdstate ),
.o_sdr_rd_valid ( o_sdr_rd_valid ),
.o_sdr_dout ( o_sdr_dout ),
.o_dbg_re ( o_dbg_re ),
.o_AXI4_BID ( o_AXI4_BID ),
.i_addr ( i_addr ),
.i_din ( i_din ),
.i_dm ( i_dm ),
.o_dout ( o_dout ),
.o_sdr_state ( o_sdr_state ),
.o_sdr_init_done ( o_sdr_init_done ),
.o_wr_ack ( o_wr_ack ),
.o_rd_ack ( o_rd_ack ),
.o_ref_req ( o_ref_req ),
.o_rd_valid ( o_rd_valid ),
.o_sdr_CKE ( o_sdr_CKE ),
.o_sdr_n_CS ( o_sdr_n_CS ),
.o_sdr_n_RAS ( o_sdr_n_RAS ),
.o_sdr_n_CAS ( o_sdr_n_CAS ),
.o_sdr_n_WE ( o_sdr_n_WE ),
.o_sdr_BA ( o_sdr_BA ),
.o_sdr_ADDR ( o_sdr_ADDR ),
.o_sdr_DATA ( o_sdr_DATA ),
.o_sdr_DATA_oe ( o_sdr_DATA_oe ),
.i_sdr_DATA ( i_sdr_DATA ),
.o_sdr_DQM ( o_sdr_DQM )
);

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hw/super6502_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd Normal file
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--------------------------------------------------------------------------------
-- Copyright (C) 2013-2023 Efinix Inc. All rights reserved.
--
-- This document contains proprietary information which is
-- protected by copyright. All rights are reserved. This notice
-- refers to original work by Efinix, Inc. which may be derivitive
-- of other work distributed under license of the authors. In the
-- case of derivative work, nothing in this notice overrides the
-- original author's license agreement. Where applicable, the
-- original license agreement is included in it's original
-- unmodified form immediately below this header.
--
-- WARRANTY DISCLAIMER.
-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
--
-- LIMITATION OF LIABILITY.
-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
-- APPLY TO LICENSEE.
--
--------------------------------------------------------------------------------
------------- Begin Cut here for COMPONENT Declaration ------
COMPONENT sdram_controller is
PORT (
i_aresetn : in std_logic;
i_AXI4_AWADDR : in std_logic_vector(23 downto 0);
i_sysclk : in std_logic;
i_sdrclk : in std_logic;
i_tACclk : in std_logic;
i_pll_locked : in std_logic;
o_dbg_ref_req : out std_logic;
o_dbg_wr_ack : out std_logic;
o_dbg_rd_ack : out std_logic;
o_dbg_n_CS : out std_logic_vector(1 downto 0);
o_dbg_n_RAS : out std_logic_vector(1 downto 0);
o_dbg_n_CAS : out std_logic_vector(1 downto 0);
o_dbg_n_WE : out std_logic_vector(1 downto 0);
o_dbg_BA : out std_logic_vector(3 downto 0);
o_dbg_ADDR : out std_logic_vector(25 downto 0);
o_dbg_DATA_out : out std_logic_vector(31 downto 0);
o_dbg_DATA_in : out std_logic_vector(31 downto 0);
o_pll_reset : out std_logic;
o_AXI4_AWREADY : out std_logic;
i_AXI4_AWVALID : in std_logic;
o_AXI4_WREADY : out std_logic;
i_AXI4_WDATA : in std_logic_vector(31 downto 0);
i_AXI4_WSTRB : in std_logic_vector(3 downto 0);
i_AXI4_WLAST : in std_logic;
i_AXI4_WVALID : in std_logic;
o_AXI4_BVALID : out std_logic;
i_AXI4_BREADY : in std_logic;
o_AXI4_ARREADY : out std_logic;
i_AXI4_ARADDR : in std_logic_vector(23 downto 0);
i_AXI4_RREADY : in std_logic;
o_AXI4_RDATA : out std_logic_vector(31 downto 0);
o_AXI4_RLAST : out std_logic;
o_AXI4_RVALID : out std_logic;
i_AXI4_AWID : in std_logic_vector(3 downto 0);
i_AXI4_AWSIZE : in std_logic_vector(2 downto 0);
i_AXI4_ARVALID : in std_logic;
i_AXI4_ARID : in std_logic_vector(3 downto 0);
i_AXI4_ARLEN : in std_logic_vector(7 downto 0);
i_AXI4_ARSIZE : in std_logic_vector(2 downto 0);
i_AXI4_ARBURST : in std_logic_vector(1 downto 0);
i_AXI4_AWLEN : in std_logic_vector(7 downto 0);
o_AXI4_RID : out std_logic_vector(3 downto 0);
o_dbg_we : out std_logic;
o_dbg_last : out std_logic;
o_dbg_addr : out std_logic_vector(23 downto 0);
o_dbg_din : out std_logic_vector(31 downto 0);
o_axi4_wrstate : out std_logic_vector(1 downto 0);
o_fifo_wr : out std_logic;
o_fifo_full : out std_logic;
o_fifo_empty : out std_logic;
o_dbg_fifo_waddr : out std_logic_vector(7 downto 0);
o_dbg_fifo_re : out std_logic;
o_dbg_fifo_raddr : out std_logic_vector(7 downto 0);
o_dbg_fifo_we : out std_logic;
o_dbg_axi4_wlast : out std_logic;
o_shift_cnt : out std_logic_vector(6 downto 0);
o_re_lock : out std_logic;
o_axi4_rastate : out std_logic_vector(1 downto 0);
o_axi4_nwr : out std_logic;
o_axi4_arlen : out std_logic_vector(7 downto 0);
o_axi4_rdstate : out std_logic_vector(1 downto 0);
o_sdr_rd_valid : out std_logic;
o_sdr_dout : out std_logic_vector(36 downto 0);
o_dbg_re : out std_logic;
o_AXI4_BID : out std_logic_vector(3 downto 0);
i_addr : in std_logic_vector(23 downto 0);
i_din : in std_logic_vector(31 downto 0);
i_dm : in std_logic_vector(3 downto 0);
o_dout : out std_logic_vector(31 downto 0);
o_sdr_state : out std_logic_vector(3 downto 0);
o_sdr_init_done : out std_logic;
o_wr_ack : out std_logic;
o_rd_ack : out std_logic;
o_ref_req : out std_logic;
o_rd_valid : out std_logic;
o_sdr_CKE : out std_logic_vector(1 downto 0);
o_sdr_n_CS : out std_logic_vector(1 downto 0);
o_sdr_n_RAS : out std_logic_vector(1 downto 0);
o_sdr_n_CAS : out std_logic_vector(1 downto 0);
o_sdr_n_WE : out std_logic_vector(1 downto 0);
o_sdr_BA : out std_logic_vector(3 downto 0);
o_sdr_ADDR : out std_logic_vector(25 downto 0);
o_sdr_DATA : out std_logic_vector(31 downto 0);
o_sdr_DATA_oe : out std_logic_vector(31 downto 0);
i_sdr_DATA : in std_logic_vector(31 downto 0);
o_sdr_DQM : out std_logic_vector(3 downto 0));
END COMPONENT;
---------------------- End COMPONENT Declaration ------------
------------- Begin Cut here for INSTANTIATION Template -----
u_sdram_controller : sdram_controller
PORT MAP (
i_aresetn => i_aresetn,
i_AXI4_AWADDR => i_AXI4_AWADDR,
i_sysclk => i_sysclk,
i_sdrclk => i_sdrclk,
i_tACclk => i_tACclk,
i_pll_locked => i_pll_locked,
o_dbg_ref_req => o_dbg_ref_req,
o_dbg_wr_ack => o_dbg_wr_ack,
o_dbg_rd_ack => o_dbg_rd_ack,
o_dbg_n_CS => o_dbg_n_CS,
o_dbg_n_RAS => o_dbg_n_RAS,
o_dbg_n_CAS => o_dbg_n_CAS,
o_dbg_n_WE => o_dbg_n_WE,
o_dbg_BA => o_dbg_BA,
o_dbg_ADDR => o_dbg_ADDR,
o_dbg_DATA_out => o_dbg_DATA_out,
o_dbg_DATA_in => o_dbg_DATA_in,
o_pll_reset => o_pll_reset,
o_AXI4_AWREADY => o_AXI4_AWREADY,
i_AXI4_AWVALID => i_AXI4_AWVALID,
o_AXI4_WREADY => o_AXI4_WREADY,
i_AXI4_WDATA => i_AXI4_WDATA,
i_AXI4_WSTRB => i_AXI4_WSTRB,
i_AXI4_WLAST => i_AXI4_WLAST,
i_AXI4_WVALID => i_AXI4_WVALID,
o_AXI4_BVALID => o_AXI4_BVALID,
i_AXI4_BREADY => i_AXI4_BREADY,
o_AXI4_ARREADY => o_AXI4_ARREADY,
i_AXI4_ARADDR => i_AXI4_ARADDR,
i_AXI4_RREADY => i_AXI4_RREADY,
o_AXI4_RDATA => o_AXI4_RDATA,
o_AXI4_RLAST => o_AXI4_RLAST,
o_AXI4_RVALID => o_AXI4_RVALID,
i_AXI4_AWID => i_AXI4_AWID,
i_AXI4_AWSIZE => i_AXI4_AWSIZE,
i_AXI4_ARVALID => i_AXI4_ARVALID,
i_AXI4_ARID => i_AXI4_ARID,
i_AXI4_ARLEN => i_AXI4_ARLEN,
i_AXI4_ARSIZE => i_AXI4_ARSIZE,
i_AXI4_ARBURST => i_AXI4_ARBURST,
i_AXI4_AWLEN => i_AXI4_AWLEN,
o_AXI4_RID => o_AXI4_RID,
o_dbg_we => o_dbg_we,
o_dbg_last => o_dbg_last,
o_dbg_addr => o_dbg_addr,
o_dbg_din => o_dbg_din,
o_axi4_wrstate => o_axi4_wrstate,
o_fifo_wr => o_fifo_wr,
o_fifo_full => o_fifo_full,
o_fifo_empty => o_fifo_empty,
o_dbg_fifo_waddr => o_dbg_fifo_waddr,
o_dbg_fifo_re => o_dbg_fifo_re,
o_dbg_fifo_raddr => o_dbg_fifo_raddr,
o_dbg_fifo_we => o_dbg_fifo_we,
o_dbg_axi4_wlast => o_dbg_axi4_wlast,
o_shift_cnt => o_shift_cnt,
o_re_lock => o_re_lock,
o_axi4_rastate => o_axi4_rastate,
o_axi4_nwr => o_axi4_nwr,
o_axi4_arlen => o_axi4_arlen,
o_axi4_rdstate => o_axi4_rdstate,
o_sdr_rd_valid => o_sdr_rd_valid,
o_sdr_dout => o_sdr_dout,
o_dbg_re => o_dbg_re,
o_AXI4_BID => o_AXI4_BID,
i_addr => i_addr,
i_din => i_din,
i_dm => i_dm,
o_dout => o_dout,
o_sdr_state => o_sdr_state,
o_sdr_init_done => o_sdr_init_done,
o_wr_ack => o_wr_ack,
o_rd_ack => o_rd_ack,
o_ref_req => o_ref_req,
o_rd_valid => o_rd_valid,
o_sdr_CKE => o_sdr_CKE,
o_sdr_n_CS => o_sdr_n_CS,
o_sdr_n_RAS => o_sdr_n_RAS,
o_sdr_n_CAS => o_sdr_n_CAS,
o_sdr_n_WE => o_sdr_n_WE,
o_sdr_BA => o_sdr_BA,
o_sdr_ADDR => o_sdr_ADDR,
o_sdr_DATA => o_sdr_DATA,
o_sdr_DATA_oe => o_sdr_DATA_oe,
i_sdr_DATA => i_sdr_DATA,
o_sdr_DQM => o_sdr_DQM);
------------------------ End INSTANTIATION Template ---------

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hw/super6502_fpga/ip/sdram_controller/settings.json Normal file
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{
"args": [
"-o",
"sdram_controller",
"--base_path",
"/home/byron/Projects/super6502/hw/super6502_fpga/ip",
"--vlnv",
{
"vendor": "efinixinc.com",
"library": "memory_controller",
"name": "efx_sdram_controller",
"version": "5.0"
}
],
"conf": {
"fCK_MHz": "200",
"tIORT_u": "2",
"CL": "3",
"DDIO_TYPE": "\"SOFT\"",
"DQ_GROUP": "2",
"ROW_WIDTH": "13",
"COL_WIDTH": "9",
"tPWRUP": "200000",
"tRAS": "44",
"tRAS_MAX": "120000",
"tRC": "66",
"tRCD": "20",
"tREF": "64000000",
"tRFC": "66",
"tRP": "20",
"SDRAM_MODE": "\"AXI4\"",
"DATA_RATE": "2"
},
"output": {
"external_source_source": [
"/home/byron/Projects/super6502/hw/super6502_fpga/ip/sdram_controller/sdram_controller_tmpl.v",
"/home/byron/Projects/super6502/hw/super6502_fpga/ip/sdram_controller/sdram_controller.v",
"/home/byron/Projects/super6502/hw/super6502_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd",
"/home/byron/Projects/super6502/hw/super6502_fpga/ip/sdram_controller/sdram_controller_define.vh"
]
},
"sw_version": "2023.1.150",
"generated_date": "2024-03-04T01:51:33.450281"
}