Merge branch '81-add-simulation' into 'AXI-Rewrite'

Resolve "Add simulation"

Closes #81

See merge request bslathi19/super6502!68

.gitignore

@@ -19,4 +19,7 @@
 
 
 *.mem
+sim_top
 
+# Allow sources.list specifically
+!*sources.list

.gitlab-ci.yml

@@ -3,6 +3,7 @@ variables:
 
 stages:
   - build
+  - sim
 
 build:
   stage: build
@@ -13,3 +14,11 @@ build:
     - source init_env.sh
     - make
 
+sim:
+  stage: sim
+  tags:
+    - linux
+  script:
+    - source init_env.sh
+    - make sim
+

.gitmodules

@@ -7,3 +7,6 @@
 [submodule "sw/toolchain/cc65"]
 	path = sw/toolchain/cc65
 	url = ../cc65.git
+[submodule "hw/super6502_fpga/src/sim/sub/verilog-6502"]
+	path = hw/super6502_fpga/src/sim/sub/verilog-6502
+	url = ../verilog-6502.git

Makefile

@@ -11,6 +11,8 @@ all: fpga_image
 fpga_image: $(INIT_HEX)
 	$(MAKE) -C hw/super6502_fpga
 
+sim: $(INIT_HEX)
+	$(MAKE) -C hw/super6502_fpga/src/sim
 
 # SW
 .PHONY: toolchain
@@ -27,6 +29,7 @@ $(HEX):
 clean:
 	$(MAKE) -C hw/super6502_fpga $@
 	$(MAKE) -C sw/$(ROM_TARGET) clean
+	$(MAKE) -C hw/super6502_fpga/src/sim clean
 
 .PHONY: distclean
 distclean: clean

hw/super6502_fpga/src/sim/Makefile

@@ -0,0 +1,26 @@
+FPGA_SRCS_LIST=../../sources.list
+SIM_SRCS_LIST=sources.list
+
+SUPER6502_FPGA_SOURCES=$(foreach file, $(shell cat $(FPGA_SRCS_LIST)), ../../$(file))
+SIM_SOURCES=$(shell cat $(SIM_SRCS_LIST))
+
+TB_NAME=sim_top
+
+COPY_FILES=addr_map.mem init_hex.mem
+
+all: waves
+
+waves: $(TB_NAME)
+	./$(TB_NAME) -fst
+
+$(TB_NAME): $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) $(COPY_FILES)
+	iverilog -g2005-sv $(FLAGS) -s $@ -o $@ $(SUPER6502_FPGA_SOURCES) $(SIM_SOURCES) -I ../../
+
+$(COPY_FILES): ../../$@
+	cp ../../$@ .
+
+.PHONY: clean
+clean:
+	rm -rf $(COPY_FILES)
+	rm -rf $(TB_NAME)
+	rm -rf sim_top.vcd

hw/super6502_fpga/src/sim/hvl/sim_top.sv

@@ -0,0 +1,103 @@
+`timescale 1ns/1ps
+
+module sim_top();
+
+localparam ADDR_WIDTH = 32;
+localparam DATA_WIDTH = 32;
+
+logic clk_100, clk_200, clk_50, clk_cpu;
+
+// clk_100
+initial begin
+    clk_100 <= '1;
+    forever begin
+        #5 clk_100 <= ~clk_100;
+    end
+end
+
+// clk_200
+initial begin
+    clk_200 <= '1;
+    forever begin
+        #2.5 clk_200 <= ~clk_200;
+    end
+end
+
+// clk_50
+initial begin
+    clk_50 <= '1;
+    forever begin
+        #10 clk_50 <= ~clk_50;
+    end
+end
+
+// clk_cpu
+// 2MHz
+initial begin
+    clk_cpu <= '1;
+    forever begin
+        // #62.5 clk_cpu <= ~clk_cpu;
+        #250 clk_cpu <= ~clk_cpu;
+    end
+end
+
+
+initial begin
+    $dumpfile("sim_top.vcd");
+    $dumpvars(0,sim_top);
+end
+
+logic button_reset;
+
+logic           w_cpu0_reset;
+logic [15:0]    w_cpu0_addr;
+logic [7:0]     w_cpu0_data_from_cpu;
+logic [7:0]     w_cpu0_data_from_dut;
+logic           w_cpu0_rdy;
+logic           w_cpu0_irqb;
+logic           w_cpu0_we;
+logic           w_cpu0_sync;
+
+cpu_65c02 u_cpu0 (
+    .phi2   (clk_cpu),
+    .reset  (~w_cpu0_reset),
+    .AB     (w_cpu0_addr),
+    .RDY    (w_cpu0_rdy),
+    .IRQ    (~w_cpu0_irqb),
+    .NMI    ('0),
+    .DI_s1  (w_cpu0_data_from_dut),
+    .DO     (w_cpu0_data_from_cpu),
+    .WE     (w_cpu0_we),
+    .SYNC   (w_cpu0_sync)
+);
+
+
+super6502_fpga u_dut (
+    .i_sysclk               (clk_100),
+    .i_sdrclk               (clk_200),
+    .i_tACclk               (clk_200),
+    .clk_cpu                (clk_cpu),
+
+    .button_reset           (button_reset),
+
+    .o_cpu0_reset           (w_cpu0_reset),
+    .i_cpu0_addr            (w_cpu0_addr),
+    .i_cpu0_data_from_cpu   (w_cpu0_data_from_cpu),
+    .o_cpu0_data_from_dut   (w_cpu0_data_from_dut),
+    .o_cpu0_rdy             (w_cpu0_rdy),
+    .o_cpu0_irqb            (w_cpu0_irqb),
+    .i_cpu0_rwb             (~w_cpu0_we),
+    .i_cpu0_sync            (w_cpu0_sync)
+);
+
+initial begin
+    button_reset <= '1;
+    repeat(10) @(clk_cpu);
+    button_reset <= '0;
+    repeat(10) @(clk_cpu);
+    button_reset <= '1;
+    repeat(4000) @(posedge clk_cpu);
+    $finish();
+end
+
+endmodule

hw/super6502_fpga/src/sim/sources.list

@@ -0,0 +1,3 @@
+hvl/sim_top.sv
+sub/verilog-6502/ALU.v
+sub/verilog-6502/cpu_65c02.v

hw/super6502_fpga/super6502_fpga.xml

@@ -1,4 +1,4 @@
-<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Sun Mar 03 2024 14:48:43" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
+<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="super6502_fpga" description="" last_change_date="Sun Mar 03 2024 17:03:26" location="/home/byron/Projects/super6502/hw/super6502_fpga" sw_version="2023.1.150" last_run_state="pass" last_run_tool="efx_pgm" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
     <efx:device_info>
         <efx:family name="Trion" />
         <efx:device name="T20F256" />