Add sdram, don't think it works though

2024-03-03 20:43:37 -08:00
parent 78dfb01bd7
commit 10a72d8e1f
17 changed files with 6256 additions and 31 deletions
--- a/hw/super6502_fpga/ip/sdram_controller/settings.json
+++ b/hw/super6502_fpga/ip/sdram_controller/settings.json
@@ -0,0 +1,44 @@
+{
+    "args": [
+        "-o",
+        "sdram_controller",
+        "--base_path",
+        "/home/byron/Projects/super6502/hw/super6502_fpga/ip",
+        "--vlnv",
+        {
+            "vendor": "efinixinc.com",
+            "library": "memory_controller",
+            "name": "efx_sdram_controller",
+            "version": "5.0"
+        }
+    ],
+    "conf": {
+        "fCK_MHz": "200",
+        "tIORT_u": "2",
+        "CL": "3",
+        "DDIO_TYPE": "\"SOFT\"",
+        "DQ_GROUP": "2",
+        "ROW_WIDTH": "13",
+        "COL_WIDTH": "9",
+        "tPWRUP": "200000",
+        "tRAS": "44",
+        "tRAS_MAX": "120000",
+        "tRC": "66",
+        "tRCD": "20",
+        "tREF": "64000000",
+        "tRFC": "66",
+        "tRP": "20",
+        "SDRAM_MODE": "\"AXI4\"",
+        "DATA_RATE": "2"
+    },
+    "output": {
+        "external_source_source": [
+            "/home/byron/Projects/super6502/hw/super6502_fpga/ip/sdram_controller/sdram_controller_tmpl.v",
+            "/home/byron/Projects/super6502/hw/super6502_fpga/ip/sdram_controller/sdram_controller.v",
+            "/home/byron/Projects/super6502/hw/super6502_fpga/ip/sdram_controller/sdram_controller_tmpl.vhd",
+            "/home/byron/Projects/super6502/hw/super6502_fpga/ip/sdram_controller/sdram_controller_define.vh"
+        ]
+    },
+    "sw_version": "2023.1.150",
+    "generated_date": "2024-03-04T01:51:33.450281"
+}